This paper presents measured results of dynamic voltage drop caused by pulse and periodic injection of spot noise. The test structure being fabricated by a 45 nm low-power process has 1024 delay probes to measure spatial distributions in response to the spot-noise generation. The test structure is the advanced version of our predecessor being fabricated by a 65-nm node, and can trace changes in the spatial distributions with time after the noise injection. The measured results are compared with SPICE simulations, in which package/socket LCR as well as power-line RC within the die is modeled. It is found that the simple model agrees well with the measured results.

This paper describes observations of supply-voltage-noise dispersion by using a test structure fabricated with a 65-nm low-power process. The test structure can capture the phenomenon in two domains: One is a space domain. The 1 kbit probes distributed uniformly over the entire test-module region detect the spread of the noise, which is induced in the center of the module. The noise is generated by simultaneous activation of 8 kbit flip-flops (FF), which are placed in a dense area. Each delay probe consists of a short buffer-chain between a pair of FFs to detect the delay shift caused by voltage drop in the area. The other is a time domain. The probes being different in the length of the buffer-chains can capture the time dependency. The measurement results have revealed how the supply-voltage-noise spreads over the entire test-module region in a very short time (sub-nsec).

This paper presents a clock-skew test module for exploring reliable clock distribution under process, voltage, and temperature (PVT) variations. The proposed test module enables direct evaluation of the following two important issues: 1) the clock-skew process variations and 2) the robustness against race problems under environmental variations such as voltages and temperatures. The test module was fabricated by using a 90-nm low-power process for system-on-chip (SoC). It contains eight blocks including H-tree blocks and clock tree synthesis (CTS)-tree blocks (i.e., blocks formed by clock-tree synthesis), each of which has 1024 flip-flop (FF) pairs with small hold-time margins. A statistical method has been developed for analyzing the measured hold-time margins of the 1024 FF pairs for 80 chips. The example of the analysis for the measured results is presented, confirming the effectiveness of the proposed test module and analysis method toward reliable design of clock distribution.

In many disciplines success depends onaccess to scarce resources, such as unique instruments. Researchon computer-supported cooperative work has contributed to the development of technologies, such as collaboratories, that broaden access to scarce scientific and engineering resources. While broader access is often applauded, little attention has been focused on the problem of equitable and efficient resource allocation in the face of increased demand created through collaboratory use. This paper, then, uses the framework of mechanism design to evaluate different resource allocation schemes (RAD, Vickery, and knapsack). Experimental results show that knapsack achieves a more equitable distribution of resources than RAD or Vickery, but that RAD and Vickery are both more efficient than knapsack. The findings highlight the need for systematic exploration of allocation mechanisms within collaboratories, where simple optimization (e.g., knapsack) is likely to produce a sub-optimal match of resources to needs. More generally, the findings illustrate the utility of experimental economic approaches in understanding issues that emerge in large-scale collaborations, such as entire scientific and engineering communities.

The crosstalk delay caused by capacitive coupling between wires on a chip is investigated by using a statistical approach and circuit simulations. Two metrics are introduced in order to evaluate an impact of the crosstalk delay on timing design in advance. The first is probabilistic coupling rate (CPR), which can be obtained by the short segment model of the aggressors. Then, the CPR roughly obeys normal distribution and its standard deviation is determined by the slew time of the victim along with the number of aggressor segments. The second is crosstalk delay normalized by the original delay without crosstalk, /spl Delta/t/sub pd//t/sub pd/. The /spl Delta/t/sub pd//t/sub pd/ is equal to 2*CPR at the maximum, and CPR on average, regardless of victim length. The two metrics in conjunction with empirical slew distribution allows us to set the appropriate crosstalk delay budget, at the prelayout stage, for reducing the possibility of the crosstalk violation found in the postlayout verification process.