Among other things, field-programmable gate arrays (FPGAs) available today contain numerous bit-serial transceivers for communication purposes. Unlike analog modulation schemes, such as quadrature amplitude modulation, bit-serial communication is relatively easy to implement in digital hardware, and is thus usually used for inter FPGA communication. In this view, only the data rate and frequency limit the bandwidth of the circuit. In order to overcome the bandwidth limit, this research proposes a pulse-width modulation (PWM) scheme for data transmission. The information is coded by modulating the length of the high and low voltage parts of the pulse. Although this approach is not new, existing PWM modulators have unsatisfactorial data rates due to their synchronous implementation nature. Therefore, this research implements both the modulator and demodulator by using asynchronous logic. The result is a proof-of-concept comprising two Terasic DE2-70 development boards and a 1 m coaxial cable. Both the PWM modulator and demodulator run at 333 MHz, and pulses are transmitted every 3 ns. Each pulse carries 3 to 4 bits of data. The experimental results indicate an achievable data rate of one gigabit per second, which is about 50 % larger than the FPGA's handbook states.

Non-trivial hardware architectures consist of a significant number of fine-grained modules that communication with each other via dedicated signal lines. In field-programmable gate arrays (FPGAs), these communication lines are provided in forms of global vertical and horizontal routing channels, and are subject to the routing process. Since the effects of physical properties on the signal skew along these lines is well understood, this paper investigates the observable effects on a signal's duty cycle. Practical experiments show that the distortion on the duty cycle progressively increases along such wires (connections) and that in the extreme case, a signal may entirely vanish.

Previous research has proposed several platforms for the direct hardware implementation of neural networks. Most of these platforms employ a small number of special-purpose processors that emulate a given number of neurons. By contrast, this paper proposes a light-weight hardware model, called time coded output (TiCO) neuron, which codes its internal activation as the duration of its output pulses. Since the implementation of such a neuron requires only about 200 logical elements, standard state-of-the-art field-programmable gate arrays may host several hundreds of neurons on a single chip. Due to its output coding and its low footprint, TiCO neurons are particularly suited for the usage in embedded systems.

Normally, research on evolutionary computation applies its algorithms to the solution or optimization of some technical or mathematical problems. But for some technical tasks, such as localization, nature seem to provides optimal solutions. This paper discusses how the barn owl auditory system can be conceptually realized on a digital system, such as a field programmable gate array. This adapted system yields a time resolution as small as 20 ps, even though it is clocked at only 85 MHz, which corresponds to a duty cycle of about 12 ns. The system achieves this result by copying the natural role model's core principles, i.e., employing a large number of simple, slowly operating processing elements, which are all connected to two passive wires, which induce only a very small additional time delay; these properties are the result of a natural evolutionary process that has taken millions of years.

The nucleus laminaris of the barn owl auditory system is quite impressive, since its underlying time estimation is much better than the processing speed of the involved neurons. Since precise localization is also very important in many technical applications, this paper explores to what extent the main principles of the nucleus laminaris can be implemented in digital hardware. The first prototypical implementation yields a time resolution of about 20 ps, even though the chosen standard, low-cost device is clocked at only 85 MHz, which leads to an internal duty cycle of approximately 12 ns.

Field-programmable gate arrays provide a very flexible implementation platform that supports the development of tamper-proof networked embedded systems. In order to achieve a secure mode of operation, many of these systems employ keyed-hash message authentication code, to provide security against intentional tampering. Since this algorithm is of high computational complexity, this paper utilizes various hardware-software co-design techniques for its implementation, and compares the results to standard software. The considered techniques vary in the degree of required design expertise and of how (software) functionalities are implemented in hardware logic.

Field-programmable gate arrays provide a flexible and easy-to-configure implementation platform that supports the development of tamper-proof networked embedded systems. Many of these systems employ the Advanced Encryption Standard algorithm in order to achieve a secure mode of operation. Since this algorithm is of a high computational complexity, this paper utilizes various hardware-software co-design techniques for its implementation. These techniques vary in the degree of required design expertise, the degree of how (software) functionalities are implemented in hardware logic, and the achievable speedup, which is about 12 to approximately four thousand.

Tapped delay lines are chain-like structures, which are able to measure short time intervals. Due to their homogeneous structure, they are particularly suited for being implemented on field-programmable gate arrays. But unfortunately, the attainable resolution in time is inherently limited to the average processing speed of the chainpsilas elements. As an alternative, this paper proposes a new architecture, called BOUNCE, in which all processing elements run in parallel. With its inherent parallelism, BOUNCE yields a resolution that depends on the variation, i.e., the differences, among the elementspsila processing speeds. The first prototype was implemented on an ALTERA StratixII 2S60 board Even though this board is clocked at only 85 MHz, the prototype yields a resolution of about 100ps.

Tapped delay lines are chain-like structures, which are able to measure short time intervals. Due to their homogeneous structure, they are particularly suited for being implemented on field-programmable gate arrays. But unfortunately, the attainable resolution in time is inherently limited to the average processing speed of the chain elements. As an alternative, this paper proposes a new architecture, called BOUNCE in which all processing elements run in parallel. With its inherent parallelism, BOUNCE yields a resolution that depends on the variation, i.e., the differences, among the elementspsila processing speeds. The first prototype was implemented on an ALTERA StratixII 2S60 board. Even though this board is clocked at only 85 MHz, the prototype yields a resolution of about 150 ps.

Print media are still very important for everyone's daily life. Current efforts are concerned with the application of the well-established offset-printing technology to other media, particularly cardboards, which require some substantial adaptations. To this end, this paper proposed a new specific pre-processing stage. This pre-processing stage can be configured by several parameters. This paper optimizes these parameter settings by using evolution strategies. It turns out that this optimization reduces the required energy and the number of wrongly generated pixels by about 15%, respectively.