This work describes a high-speed simulation technique of analog circuits which is based on the use of state- space equations and an explicit integration method parallelised on a multiprocessor architecture. The integration step of such method is smaller than the one required by an implicit simulation technique based on Newton-Raphson iterations. However, given that explicit methods do not require the computation of timeconsuming matrix factorizations, the overall simulation time is reduced. The technique described in this work has been implemented on a NVIDIA general purpose GPU and has been tested simulating the Gaussian filtering operation performed by a smart CMOS image sensor. Such devices are used to perform computation on the edge and include built-in image processing functions. Among those, the Gaussian filtering is one of the most common functions, since it is a basic task for early vision processing. These smart sensors are increasingly complex and hence the time required to simulate them during their design cycle is also larger and larger. From a certain imager size, the proposed simulation method yields simulation times two order of magnitude faster that an implicit method based tool such us SPICE.

This paper presents the first RISC-V vector processor design aimed at microcontrollers that uses the new RISC-V `V' extension for vectors, part of the open-source RISC-V instruction set architecture (ISA). Being aimed at small embedded devices, it demonstrates a simpler method of parallel execution than traditional vector architectures to minimise logic. It has been synthesised for testing on an FPGA at 50MHz. Typical vector-compatible applications have been used as benchmarks. Performance has been improved by up to 5.8x for the demonstrated applications relative to a comparable scalar RISC-V processor, for an increase in FPGA resource utilisation of at most 2.6x.

This paper presents a new high-performance technique to parallelise numeric integration of large VLSI interconnect analog models on a general purpose GPU. The technique is based on the combination of space-state formulation with an explicit integration method based on the Adams-Bashforth second order formula. The paper studies the stability of the variable step explicit method and proposes a technique to guarantee integration stability specifically for interconnect systems. Although explicit methods require smaller integration steps compared to those of the traditional implicit techniques, they avoid the complex calculations inherent to implicit integration. The proposed approach is demonstrated using an RC VLSI interconnect model and results are compared to those achieved by Ngspice, a state-of-the-art implicit integration solver, implemented on the same parallel hardware. The results show that the speed-up of the parallelised explicit solution reaches one order of magnitude for large systems and is increasing with the circuit size.

This contribution presents a new Modified Compressed Sparse Row (MCSR) format designed for multi-core FPGA-based hardware accelerators for the calculation of Sparse Matrix Vector Multiplication (SMVM). Current state-of-the-art methods suffer from memory bandwidth bottlenecks affecting the speed of parallel SMVM. The salient feature of the proposed MCSR format is that an extension of Hu's scheduling algorithm has been adopted to relocate the non-zero entries of the sparse matrix to ensure a continuous flow of data at each core, thus eliminating redundant memory requests and unnecessary intermediate result storage. Consequently, effects of the memory bandwidth bottleneck are reduced. Dedicated Multiplication and Accumulation (MAC) cores have been used in the experiments presented in this paper. The correct functionality of the proposed method is verified through Modelsim simulations. A thorough investigation of the effectiveness of the new format was carried out using a number of case studies with variable sparsities and matrix sizes, resulting to a speedup that reaches up to four orders of magnitude compared with an Intel i7 CPU.

This paper describes an efficient numerical solution to speed up transient simulations of analog circuits on a many-core computer. The technique is based on an explicit integration method, parallelised on a multiprocessor architecture. Although the integration step is smaller than the required one by traditional simulation methods based on Newton-Raphson iterations, explicit methods do not require to compute complex calculations such us matrix factorizations, which lead to long CPU simulation times. The proposed technique has been implemented on a NVIDIA GPU and has been demonstrated simulating Gaussian filtering operations performed by a CMOS vision chip. These type of devices, which are used to perform computation on the edge, include built-in image processing functions, turning them into very complex and time consuming circuits during their design. The proposed method is faster that Ngspice for different image sizes, and for 128 x 128 pixels image size it achieves a speed up of two orders of magnitude.

This paper presents a technique to accelerate transient simulations of analog circuits using an explicit integration method parallelised on a many-core computer. Usual methods used by SPICE-type simulators are based on Newton-Raphson iterations, which are reliable and numerically stable, but require long CPU processing times. However, although the integration time step in explicit methods is smaller than that used in implicit methods, this technique avoids the calculation of time-consuming computations due to the Jacobian matrix inversion. The proposed method uses an explicit integration scheme based on the fourth order Adams-Bashforth formula. The algorithm has been parallelised on a NVIDIA general purpose GPU using the CUDA programming model. As a case study, the RC ladder model of a VLSI interconnect is simulated on a general purpose graphic processing unit and the achieved performance is then evaluated against that of a multiprocessor CPU. The results show that the proposed technique achieves a speedup of one order of magnitude in comparison with implicit integration techniques executed on a CPU.

NBTI is becoming one of the major circuit reliability issues in nano-scale technologies. BTI can cause a threshold voltage shift in CMOS devices and consequently increase circuit delay. This paper proposed a novel ageing aware approach to improve circuit's lifetime. The vulnerable circuit paths against ageing effects are isolated. In addition, minimum area overhead is consumed by adopting proposed synthesis algorithm. The simulation results show that the proposed approach can save up to 67.7% area compared with the conventional over-design technique.

Electronic devices with power-constrained embedded systems are used for a variety of IoT applications, such as geo-monitoring, parking sensors and surveillance, which may tolerate few errors and may not be constrained by a strict error detection latency requirement. In this poster, we propose a novel low power online error monitoring technique that produces an alarm signal when systematic erroneous behaviour has occurred over a pre-defined time interval. A monitoring architecture monitors the signal probabilities of the logic cones concurrently to its normal operation and compares them on-chip against the signature of error-free behaviour. Results on a set of the EPFL'15 benchmarks show an average error coverage of 82.9%% of errors induced by stuck-at faults, with an average area cost of 1.2% and an error detection latency of [0.01, 3.3] milliseconds.

Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not all workloads are equally susceptible to errors. In this paper, we present a low power fault tolerance design technique that selects and protects the most susceptible workload. We propose to rank the workload susceptibility as the likelihood of any error to bypass the logic masking of the circuit and propagate to its outputs. The susceptible workload is protected by a partial Triple Modular Redundancy (TMR) scheme. We evaluate the proposed technique on timing-independent and timing-dependent errors induced by permanent and transient faults. In comparison with unranked selective fault tolerance approach, we demonstrate a) a similar error coverage with a 39.7% average reduction of the area overhead or b) a 86.9% average error coverage improvement for a similar area overhead. For the same area overhead case, we observe an error coverage improvement of 53.1% and 53.5% against permanent stuck-at and transition faults, respectively, and an average error coverage improvement of 151.8% and 89.0% against timing-dependent and timing-independent transient faults, respectively. Compared to TMR, the proposed technique achieves an area and power overhead reduction of 145.8% to 182.0%.

This paper provides the first analysis of process variation effect on the adiabatic logic combined with near-threshold operation. One of the significant concerns is whether reliable performance is retained. We find that typical variations of process parameters do not affect error-free operation at the minimum-energy frequency. Monte Carlo simulations of a 4- bit full adder using ECRL logic with 0.45 V supply voltage show that, in the presence of typical process variations, energy consumption of the circuit operating at 25 MHz increases by 10.2% in the worst case while a 100% error-free operation is maintained. The maximum operating frequency(208 MHz) is reduced to nearly half of the nominal value(385 MHz). To further improve the robustness of the adder against process variation, a bit-serial adiabatic adder is considered with an even lower energy consumption per cycle.

Dynamic thermal management is an increasingly critical and complex part of the run-time management of many-core systems. Methods of controlling temperature include thread migration, dynamic voltage and frequency scaling and power gating using various strategies and combinations of each. In the PRiME project we are developing run-time management systems to sustain the scaling of many-core systems. As part of this development we are investigating the relative benefits of different thermal management strategies by co-simulating a Modellica model of the characteristics of a many-core device with a discrete Event-B model of the run-time manager. The results enable us to efficiently design more elaborate experiments on real hardware platforms in order to validate the run time management.

In this paper, we present a novel fault tolerance design technique, which is applicable at the register transfer level, based on protecting the functionality of logic circuits using a probabilistic fault model. The proposed technique selects the most susceptible workload of combinational circuits to protect against probabilistic faults. The workload susceptibility is ranked as the likelihood of any fault to bypass the inherent logical masking of the circuit and propagate an erroneous response to its outputs, when that workload is executed. The workload protection is achieved through a Triple Modular Redundancy (TMR) scheme by using the patterns that have been evaluated as most susceptible. We apply the proposed technique on LGSynth91 and ISCAS85 benchmarks and evaluate its fault tolerance capabilities against errors induced by permanent faults and soft errors. We show that the proposed technique, when it is applied to protect only the 32 most susceptible patterns, achieves on average of all the examined benchmarks, an error coverage improvement of 98% and 94% against errors induced by single stuck-at faults (permanent faults) and soft errors (transient faults), respectively, compared to a reduced TMR scheme that protects the same number of susceptible patterns without ranking them.

This paper presents the concept of a bilayer graphene transistor using a floating gate to achieve the necessary threshold potential required for symmetrical transfer characteristics in complementary inverters. Using the charge injected into the floating-gate, the threshold voltage of the channel can be controlled. The control of the channel's electrostatic doping using a floating-gate is exploited to simulate an inverter which shows a symmetrical transfer characteristic centred at an input voltage of Vdd/2.

In an energy harvester powered wireless sensor node, the energy harvester is often the only energy source, therefore it is crucial to configure the microcontroller and the sensor node so that the harvested energy is used efficiently. This paper presents a response surface model (RSM) based design space exploration and optimisation of a complete wireless sensor node system. In our work the power consumption models of the microcontroller and the sensor node are defined based on their digital operations so that the parameters of the digital algorithms can be optimised to achieve the best energy efficiency. In the proposed technique, SystemC-A is used to model the system's analogue components as well as the digital control algorithms implemented in the microcontroller and the sensor node. A series of simulations are carried out and a response surface model is constructed from the simulation results. The RSM is then optimised using MATLAB's optimisation toolbox and the results show that the optimised system configuration can double the total number of wireless transmissions with fixed amount of harvested energy. The great improvement in the system performance validates the efficiency of our technique.

Vibration energy harvesting systems pose significant modeling and design challenges due to their mixed-technology nature, extremely low levels of available energy and disparate time scales between different parts of a complete harvester. An energy harvester is a complex system of tightly coupled components modeled in the mechanical, magnetic, as well as electrical analog and digital domains. Currently available design tools are inadequate for simulating such systems due to prohibitive CPU times. This paper proposes a new technique to accelerate simulations of complete vibration energy harvesters by approximately two orders of magnitude. The proposed technique is to linearize the state equations of the system's analog components to obtain a fast estimate of the maximum step-size to guarantee the numerical stability of explicit integration based on the Adams-Bashforth formula. We show that the energy harvester's analog electronics can be efficiently and reliably simulated in this way with CPU times two orders of magnitude lower than those obtained from two state-of-the-art tools, VHDL-AMS and SystemC-A. As a case study, a practical, complex microgenerator with magnetic tuning and two types of power-processing circuits have been simulated using the proposed technique and verified experimentally.

Using wireless communication and energy harvesting in automobiles might have significant advantages considering dependability (no wires and contacts) and weight (no cable tree). In this paper, we give a brief overview of the related technologies, surrounding conditions, and methods for design and optimization. As examples, we focus on methods for harvesting kinetic energy and wireless transmission in a tire pressure metering system (TPMS).

This paper proposes a linearised state-space technique to accelerate the simulation of tunable vibration energy harvesting systems by at least two orders of magnitude. The paper provides evidence that currently available simulation tools are inadequate for simulating complete energy harvesting systems where prohibitive CPU times are encountered due to disparate time scales. In the proposed technique, the model of a complete mixed-technology energy harvesting system is divided into component blocks whose mechanical and analogue electrical parts are modelled by local state equations and terminal variables while the digital electrical part is modelled as a digital process. Unlike existing simulation tools that use Newton-Raphson method, the proposed technique uses explicit integration such as Adams-Bashforth method to solve the state equations of the complete energy harvester model in short simulation time. Experimental measurements of a practical tunable energy harvester have been carried out to validate the proposed technique.

This contribution proposes syntax extensions to SystemC-A that support mixed-technology system modelling where components might exhibit distributed behaviour modelled by partial differential equations. The important need for such extensions arises from the well known modelling difficulties in hardware description languages where complex electronics in a mixed-technology system interfaces with distributed components from different physical domains, e.g. mechanical, magnetic or thermal. A digital MEMS accelerometer with distributed mechanical sensing element is used as a case study to illustrate modelling capabilities offered by the proposed extended syntax of SystemC-A.

This contribution presents a novel methodology for automated optimal layout synthesis of MEMS systems embedded in electronic control circuitry from user defined high-level performance specifications and design constraints. The proposed approach is based on simulation-based optimization where automated configuration selection for electronic blocks and synthesis of mechanical layouts are coupled with calculations of optimal design parameters. The underlying dedicated MEMS simulator supports distributed mechanical dynamics to enable accurate performance prediction of critical mechanical components, such as acceleration sensing elements which form an essential part of the mixed-technology control loop.

A novel frequency domain excision filter for use in front of broadband adaptive beamformer systems is presented. The proposed frequency domain excision filter uses image processing techniques to determine the excision threshold such that only narrowband interference is removed from the received signal. By pre-excising the received signal of narrowband interference the adaptive beamformer only has to remove partialband or broadband interferers. This frees up degrees of freedom (DoF) in the adaptive beamformer in mixed interference environments allowing for a greater interference suppression capability. The proposed pre-excision system is simulated using a constrained space-time adaptive processor as well as a constrained sub-optimal space-frequency adaptive processor. It is shown that when pre-excision is used in front of a beamformer the total number of interference sources that can be simultaneously rejected is increased as long as the beamformer's DoF are exceeded by narrowband interference.

This paper proposes, for the first time, an automated energy harvester design flow which is based on a single HDL software platform that can be used to model, simulate, configure and optimise energy harvester systems. A demonstrator prototype incorporating an electromagnetic mechanical-vibration-based micro-generator and a limited number of library models has been developed and a design case study has been carried out. Experimental measurements have validated the simulation results which show that the outcome from the design flow can improve the energy harvesting efficiency by 75%.

This paper presents a new carbon nanotube transistor (CNT) modelling technique which is based on an efficient numerical piece-wise non-linear approximation of the non-equilibrium mobile charge density. The technique facilitates the solution of the self-consistent voltage equation in a carbon nanotube such that the CNT drain-source current evaluation is accelerated by more than three orders of magnitude while maintaining high modelling accuracy. The model is currently limited to ballistic transport but can be extended to non-ballistic modes of transport when a suitable theory is developed while researchers study phenomena that sometimes prevent electrons in a carbon nanotube from going ballistic. Our results show that while the accuracy and speed of the proposed model vary with the number of piece-wise segments in the mobile charge approximation, it is possible to obtain a speed-up of more than 1000 times while maintaining the accuracy within less than 2% in terms of average RMS error compared with the state of the art theoretical reference CNT model implemented in FETToy. This numerical efficiency makes our model particularly suitable for implementation in circuit-level, eg. SPICE-like, simulators where large numbers of such devices may be used to build complex circuits.

This paper presents an integrated approach to energy harvester modelling and performance optimisation where the complete mixed physical-domain energy harvester system (micro generator, voltage booster, storage element and load) can be modelled and optimised in a systematic manner using one simulation platform. We developed an accurate HDL model for the energy harvester and demonstrated its accuracy by validating it experimentally and comparing it with recently reported models. To address the performance loss due to the close mechanical-electrical interaction that takes place in energy harvesters, we proposed a holistic methodology to the energy harvester optimisation based on the HDL model. The effectiveness of employing such an approach has been demonstrated by showing that it is possible to improve vibration-based energy harvester efficiency (energy delivered to load/harvested energy) by 30% through optimising the micro-generator size and the voltage booster circuit components.

This paper introduces a novel numerical carbon nanotube transistor (CNT) modelling approach which brings in a flexible and efficient cubic spline non-linear approximation of the non-equilibrium mobile charge density. The spline algorithm creates a rapid and accurate solution of the numerical relationship between the charge density and the self-consistent voltage, which leads to the speed-up of deriving the current through the channel without losing much accuracy. This modelling method also allows the flexibility of choosing different cubic spline intervals which may affect the performance of the model, but it is still capable of obtaining an acceleration of more than a 100 times while maintaining the accuracy within less than 1.5% normalised RMS error compared with previous reported theoretical modelling approach. The model has been proved working as transistors in a logic inverter implemented using VHDL-AMS and simulated in SystemVision, which shows the availability of implementing a circuit-level simulators with our proposed model. Additionally, although this model is originally based on the ideal ballistic transport characteristics, it shows good flexibility that the extension with numbers of non-ballistic features are certainly acceptable.

A new methodology is presented to assure numerically reliable integration of the magnetisation slope in the Jiles-Atherton model of ferromagnetic core hysteresis. Two HDL implementations of the technique are presented, one in SystemC and the other in VHDL-AMS. The new model uses timeless discretisation of the magnetisation slope equation and provides superior accuracy and numerical stability especially at the discontinuity points that occur in hysteresis. Numerical integration of the magnetisation slope is carried out by the model itself rather than by the underlying analogue solver. The robustness of the model is demonstrated by practical simulations of examples involving both major and minor hysteresis loops

A new methodology is presented to assure numerically reliable integration of the magnetization slope in the Jiles-Atherton model of ferromagnetic core hysteresis. Two hardware description language (HDL) implementations of the technique are presented: one in SystemC and the other in very-high-speed integrated circuit (VHSIC) HDL (VHDL) analog and mixed signal (AMS). The new model uses timeless discretization of the magnetization slope equation and provides superior accuracy and numerical stability especially at the discontinuity points that occur in hysteresis. Numerical integration of the magnetization slope is carried out by the model itself rather than by the underlying analog solver. The robustness of the model is demonstrated by practical simulations of examples involving both major and minor hysteresis loops

In this paper, a modified model of ferromagnetic hysteresis suitable for mixed-signal simulations in VHDL-AMS is presented. The aim of this paper is to demonstrate how a numerically stable and accurate implementation of the Jiles-Atherton model can be achieved using a 4th order Runga-Kutta integration of the derivative of magnetization with respect to the field strength (H). While most SPICE-like implementations require inconvenient integration in time to obtain the magnetization derivative, our approach is more general as it does not rely on the underlying differential equation solver for this purpose. The model addresses the non-physical situation of negative BH slopes and proposes an alternative implementation of the anhysteretic function using a polynomial approximation of the Langevin function for low signal levels and a new function with no discontinuities. Model efficiency is improved by monitoring the change in H and only activating the integration function when H changes by a specified amount.

We present the concept of a distributed, web-based electronic design framework. The salient feature of our system is the extension of the client-server architecture to two-tiers, with the web server serving client requests whilst acting as client to the tool servers. In the sample application of the framework, developed in Java, any of the servers can be based on Linux, MS Windows or SunSPARC server. The web server that has been used to demonstrate the framework for on-line access to VAMS (a VHDL-AMS parser) and Avant! HSPICE is currently available for Linux but has been developed with a truly platform independent implementation in mind.

A formal definition of the general VHDL-AMS analogue system has been proposed to relate the way in which the language affects the specification of a non-linear discontinuous analogue system. It has been suggested to model the break set as a separate system in order to facilitate the interaction between the analogue equation set and the digital abstract machine. The significance of the proposed model is that it may be used in semantic validation of VHDL-AMS description and may also facilitate mixed-signal equation formulation for an underlying VHDL-AMS simulator.

A new approach to mixed-signal circuit interfacing based on fuzzy logic models is presented. Due to their continuous rather than discrete character fuzzy logic models offer a significant improvement compared with the classical D-A interface models. Fuzzy logic D-A interfaces can represent the boundary between the digital and analogue worlds accurately without a significant loss of computational efficiency. The potential of mixed-signal signal interfacing based on fuzzy logic is demonstrated by an example of spike propagation from the digital to analogue world. A model of inertial propagation delay and non-linear DC gain suitable for fuzzy logic gates is also suggested.