This short paper presents a framework for periodic execution of task-flow graphs that enables schedulability analysis of the communication requirements. The analysis performs the steps of segmenting messages, assigning the segments to specific links and time intervals, and ordering them within the intervals to generate node switching schedules that provide contention-free message routing at run-time. The analysis is also used to integrate task allocation with message routing using a contention-based objective function. Usefulness of the proposed scheme in ensuring guaranteed communication performance is demonstrated by an appropriate example.>

Article Scheduling pipelined communication in distributed memory multiprocessors for real-time applications Share on Authors: Shridhar B. Shukla Code EC/Sh, Dept. of Elect. & Computer Engineering, Naval Postgraduate School, Monterey, CA Code EC/Sh, Dept. of Elect. & Computer Engineering, Naval Postgraduate School, Monterey, CAView Profile , Dharma P. Agrawal Computer Systems Laboratory, Dept. of Elect. & Computer Engineering, North Carolina State University, Raleigh, NC Computer Systems Laboratory, Dept. of Elect. & Computer Engineering, North Carolina State University, Raleigh, NCView Profile Authors Info & Claims ISCA '91: Proceedings of the 18th annual international symposium on Computer architectureApril 1991 Pages 222–231https://doi.org/10.1145/115952.115975Online:01 April 1991Publication History 19citation274DownloadsMetricsTotal Citations19Total Downloads274Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

A flexible, fault-tolerant architecture to perform 2-D convolution of images for kernels of arbitrary shapes and sizes is proposed. The convolved image is output online as the input image is generated and received, providing optimal turnaround time. The regularity of the computation and the raster-scan input of pixels are used to pipeline computations as well as memory operations. Throughput of (kl/u) is achieved for a variety of kernel sizes with a k*l array of multiply-accumulate cells, where u is the time for a single fixed-point multiply-accumulate operation. It is shown that by queuing accesses at memory modules the limitation placed by access time on the throughput can be removed. Larger, as well as smaller kernels can be accommodated on a fixed-size array with a single pass of the image and a minor change in the computation flow. The host enjoys absence of any control overhead and only has to supply the pixels and collect the output pixels in simple raster-scan fashion for any kernel size.>