This work presents an 876-MHz pulse-driven MEMS oscillator based sub-sampling wake-up receiver (WuRx) to achieve both low power and higher sensitivity. It employed 1) pulse-driven MEMS oscillator to lower the LO power; 2) 12-path sub-sampling mixer-first architecture to lower the energy needed for down-conversion; 3) baseband complex filter to support OOK/FSK modulation with good SIR rejection; 4) Transformer-based matching network to achieve passive gain. The WuRx is fabricated in TSMC 40nm CMOS technology, occupying a core area of 1.73 mm2(excluding MEMS resonator), and it realizes a sensitivity of -79/-73 dBm for OOK/FSK demodulation, respectively, while limiting the system power consumption to 579.5 μW at the continuous mode with the data rate of 160 kbps, and only 900 nW with the duty cycle ratio of 0.14% at 64 bps under 0.8-V supply voltage. In addition, the best SIR of -20 dB at an offset frequency of 1 MHz is achieved.

This paper presents a sampling fractional-N PLL employing phase interpolation embedded within linear slope generator (LSG), obviating the need for a digital-to-time converter (DTC) and RF time-domain phase interpolation (PI). Thus, the phase dithering can be achieved with only a quad-phase divider and LSG to synthesize fractional-N frequencies. By realizing large phase detector (PD) gain through the proposed architecture, it achieves an in-band phase noise of -110.4 dBc/Hz and reference spur of -74 dBc/Hz. Fabricated in 65-nm CMOS, the 5.7~5.9 GHz PLL achieves -247.1 dB FOM with 4.8-mW power consumption.

This paper presents a MEMS-based wake-up receiver (WuRX) operating at 825 MHz, with low-power and high-sensitivity. To enhance selectivity and interference rejection, a high-Q MEMS resonator is incorporated, co-designed with the low noise amplifier (LNA) to implement resonant noise matching (RNM), providing passive gain to mitigate the input-referred noise. The receiver is implemented in TSMC 65nm CMOS technology, achieving a sensitivity of −70 dBm at 10-3BER while consuming a mere 2.83 µW of power at a 1 V power supply. Additionally, it attains a SIR of 20 dB at a 2 MHz offset from the center frequency.

An ultra-lower power (ULP) MEMS-based FSK transmitter is implemented in 65 nm CMOS. The transmitter operates in ISM-915 MHz band using a binary FSK modulator employing the high-Q dual microelectromechanical system (MEMS) resonators. The transmitter using an adaptive fast switching binary FSK modulator generates FSK signals in 915 MHz band with -8.2 dBm output power, supporting up to 10 Mb/s data rate. The phase noise (PN) of the FSK modulator was measured for each of the two different operation frequencies, achieving -139.4dBc/Hz and -138.7dBc/Hz at a 1-MHz offset at 911.9 MHz and 923.1 MHz, respectively. At 10 Mb/s, the transmitter consumes 753 pW, which translates to energy-efficiency of 75.3 pJ/b.

Wearable Artificial Intelligence-of-Things (AIoT) devices demand smart gadgets that are both resource and energy-efficient. In this paper, we explore efficient implementation of binary convolutional neural network employing function merging and block reuse techniques. The hardware implemented in field programmable gate array (FPGA) platform can classify ventricular beat in electrocardiogram achieving accuracy of 97.5%, sensitivity of 85.7%, specificity of 99.0%, precision of 92.3%, and F1-score of 88.9% while consuming only 10.5-μW of dynamic power dissipation.

This paper proposes two spin orbit torque nonvolatile static random-access memories (SOT-NVSRAMs) with reduced area overhead. One of the proposed cells comprises nine transistors (9T) and a pair of complementary SOT-MTJs and the other comprises seven transistors (7T), two MOM diodes stacked over a pair of complementary SOT-MTJs. The proposed 7T cell has only one overhead transistor compared to the standard 6T SRAM cell, achieving at least 50% reduction compared to other SOT-NVSRAM designs in the literature. Moreover, the always complementary MTJs aid to increase the read margin and speed, leading to at least 20% lower restore energy of our proposed 9T cell compared to others. Furthermore, the two SOT-MTJs are written serially resulting in at least 32% lower store energy of both designs than the counterparts in the literature. In addition, the two SOT-MTJs are totally disconnected from the 6T cell in the nominal SRAM operation, which aids in maintaining the conventional SRAM high performance. Our proposed cell achieves at least 2.2x and 1.9x improvement in a figure-of-merit defined as energy and area product compared to its counterparts in the literature.

In this demonstration, we present a non-invasive, real-time lung imaging system based on the electrical impedance tomography (EIT) technique. EIT is a medical imaging technique based on the electrical properties, i.e. resistivity and permittivity of tissues and organs. This demo is based on an EIT system-on-chip that utilizes frequency division multiplexing scheme to improve the throughput by 10, allowing clinicians to identify and prevent mechanical pulmonary injury during lung ventilation.

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

This paper proposes a low-noise digital-to-frequency converter (DFC) for fractional-N frequency synthesis. The DFC first employs a subharmonic injection-locked ring oscillator (ILRO) to generate low phase noise, high-frequency fixed reference from a crystal oscillator (XO). AΣ modulator (AΣM) and accumulator are then applied to perform phase randomization and rotation around the multiphase outputs of the ILRO. This modulates the output frequency, while the rotation ensuring the range and linearity of the DFC. Meanwhile, clocking the AΣM at high frequency greatly suppresses the quantization noise, enabling a wide loop bandwidth for the subsequent phase-locked loop stage. Implemented in UMC CMOS 65-nm technology, the proposed DFC occupies an area of 0.257 mm2, and is capable of generating frequencies from 390 to 640 MHz with resolution finer than 0.3 kHz. The in-band phase noise is lower than -120 dBc/Hz at 100 kHz, tracking well with the noise performance of the XO. The shaped high-frequency quantization noise only appears beyond 20-MHz frequency offset.

This paper proposes two enhanced architectures for spin-orbit torque nonvolatile flip-flop (SOT-NVFF), namely, parallel programming scheme (pSOT-NVFF) and series programming scheme (sSOT-NVFF). At given SOT magnetic tunnel junction (SOT-MTJ) technology, the pSOT-NVFF achieves 29% lower backup energy with nearly 50% shorter backup delay compared with previous parallel architectures and the sSOT-NVFF offers at least 42% lower backup energy with 52% higher speed compared with others. Further analysis of the two proposed architectures showed a preferred window of operation for each architecture as a function of heavy metal electrode resistance (RHM). In particular, sSOT-NVFF is preferred, from speed and energy perspectives, for SOT-MTJs with small RHM(i.e., hundreds of Ω to tens of kQ), while pSOT-NVFF is preferred for SOT-MTJs with large RHMin the range of hundreds of kQ. Further study indicates that our NVFF is robust, stable, and functional even with process variations.

Freezing of gait (FoG) is a sudden and episodic inability to generate effective stepping among Parkinson's disease patients. It poses a risk for falls and deteriorates a patient's quality of life. Aid is sought after by the implementation of wearable systems that detect FoG and provide biofeedback cues in real-time. Detection is predominantly attempted with patient-independent classifiers which have difficulties to account for some patient's inimitable walking styles. Such gait peculiarities can be addressed with patient-adaptive classifiers. However, the patient-specific adaptations proposed thus far are retrospective and require a patient's labeled data. We propose to provide patient adaptivity in real-time through semi-supervised neural networks which exploit the stream of unlabeled data generated during usage. Using supervised learning, a patient-independent neural network is designed to serve as a base model. Upon a new patient's utilization of the system, the base model's parameters are adapted in real-time through unsupervised learning from the generated stream of unlabeled data. On average, patient adaptivity augmented sensitivity by 4.58% for the price of 0.59% in specificity. Moreover, it accounted for inimitable walking styles of patients that had been inadequately classified by the patient-independent base model. For such patients, sensitivity increased up to 42.01%. The overall patient-adaptive classifier resulted in 95.90% and 93.05% in sensitivity and specificity, respectively.

A mixed-signal adaptive filter is proposed which can work with level-crossing ADC to maintain its energy efficiency and signal quality even under powerline interference. The adaptive filter adopts a novel phase and amplitude tracking method which does not require multibit multiplication as the conventional least mean square (LMS) adaptive filter does. It tracks the 60 Hz interference and generate an analog compensation signal to cancel it. This technique improves the powerline interference rejection at 60Hz by 28dB. From MATLAB simulation, it effectively reduces the unnecessary sampling caused by powerline interference of the LC-ADC by 94.4%.

In this paper, we proposed an improved true random number generator (TRNG), which comprises a low-bias hardware random number generator (HRNG) and a scrambler based on linear-feedback shift register (LFSR). The HRNG reduces both DC offset from the noise sources and offset voltage from the comparator to generate low-bias bitstream. The LFSR-based scrambler further reduces the bias to zero without sacrificing the throughput rate. Randomness quality is verified by Monte Carlo simulations using the randomness test suite.

This paper presents a mostly digital IR UWB transceiver operating in 0~960 MHz frequency range for low power wearable and implantable biomedical devices. The UWB transmitter adopts a carrier-less pulse generator with BPSK modulation, and achieves energy efficiency of 100 pJ/pulse. Intermittent operation is adopted by the receiver to save power which consumes about 600 μW at 1 Mbps. The timing window of data coming is provided by a SAR DLL, which could retime the receiver clock to synchronize with the received data. This transceiver is implemented in 0.35 μm CMOS process and occupies a core area smaller than 0.8 mm2.

The University LSI Design Contest has been conceived as a unique program at ASP-DAC. The purpose of the contest is to encourage research in LSI design at universities and its realization on a chip by providing opportunities to present and discuss the innovative and state-of-the-art design. The scope of the contest covers circuit techniques for (1) Analog / RF / Mixed-Signal Circuits, (2) Digital Signal Processer, (3) Microprocessors, (4) Custom Application Specific Circuits / Memories, and methodologies for (a) Full-Custom / Cell-Based LSIs, (b) Gate Arrays, (c) Field Programmable Devices. This year, the University LSI Design Contest Committee received 19 designs from five countries/areas, and selected 10 designs out of them. The selected designs will be disclosed in Session 1A with four-minute presentations, followed by live discussions in front of their posters. For the two outstanding designs, The Best Design Award and The Special Feature Award will be presented in the banquet. We sincerely acknowledge the other contributions to the contest, too. It is our earnest belief to promote and enhance research and education in LSI design in academic organizations. Please come to the University LSI Design Contest and enjoy the stimulating discussions.

This paper presents a fully integrated 2-channel beamformer for 3-5 GHz impulse-based ultra-wideband (IR-UWB) receiver. A true time delay (TTD) element with optimized cutoff frequency and active loss compensation is proposed to provide large continuous time delay tuning with reduced chip size and power consumption. Each beamforming channel has a measured peak gain of 18.5 dB and a continuous time delay between 0-255 ps. The proposed beamformer can provide maximum scan angle of up to ±60° for two antennas with 8 cm spacing. The whole beamformer consumes 38 mA from a 1.8V DC power supply.

The rapid reduction in critical dimension of integrated circuits has lead to substantial mask data expansion for mask design based on traditional model-based full-chip optical proximity correction (OPC). Conventional EPE-OPC is mainly based on edge placement error (EPE) without consideration of its effect on circuit performance; often resulting in an overcorrected OPC mask with little improvement in circuit performance at the expense of much higher cost. In this paper, a performance-based OPC (PB-OPC) methodology is proposed taking into account both performance and cost. A less complex mask is generated based on the performance matching criteria. The framework exploits thein situestimated postlithography performance deviation error to drive the customized mask design algorithm. In particular, device PB-OPC (DPB-OPC) was deployed to systematically synthesize both polysilicon and diffusion masks by using mean drive current deviation as the controlled performance index. The proposed approach is validated via detailed simulation using 65-nm foundry libraries and IEEE International Symposium on Circuits and Systems 1985 (ISCAS'85) benchmark circuits. When compared to conventional performance-aware EPE-OPC approach, the proposed DPB-OPC achieved 34% average reduction in mask size and up to 13.5% reduction in mean drive current deviation within reasonable run time.

Along the continued shrinking of critical dimension (CD), the optical proximity correction (OPC) scheme inevitably becomes more aggressive and results in greater mask complexity and cost. Conventional OPC are edge-placement-error (EPE) driven without considering the effect of correction on circuit performance at all. We propose a performance-based OPC (PB- OPC) framework that employs a much simpler mask correction algorithm based on the real-time estimated device performances. When compared to the conventional OPC approach, our PB-OPC achieved 33 to 93% reduction in mask MEBES size and closer circuit performance matching to the design intent.

A novel multi-band low noise amplifier (LNA) that allows simultaneous reception of signals from several wireless standards is designed and implemented using a 0.18-μm CMOS technology. The circuit topology consists of a 3-stage wideband LNA and 2 notch filters. The designed LNA can provide concurrent three bands over 0.935~5.825 GHz with measured gain (S21) of 15~24 dB, input reflection ratio (S11) of -35~-7 dB, noise figure (NF) of 4.4~4.78 dB, and 3rdorder input intercept point (IIP3) of -15.3~-12.4dBm respectively. In addition, a minimum 8 dB of inter-band gain suppression is achieved. This work has achieved a better figure of merit (FOM) than other related works, in terms of gain, noise figure and power consumption trade-offs.