EDBT 2026 Demo / reviewers in the wild / expert
Jialin Dou
dblp:61/2688
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 77% Performance modeling and evaluation · 23% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › parallelization
thread-level speculation |
0.1 | 1 | 2007 | A compiler cost model for speculative parallelization · ACM Trans. Archit. Code Optim. 2007 |
Parallel and multicore computing
speculative parallelization |
0.1 | 1 | 2007 | A compiler cost model for speculative parallelization · ACM Trans. Archit. Code Optim. 2007 |
Performance modeling and evaluation
performance prediction |
0.0 | 1 | 2007 | A compiler cost model for speculative parallelization · ACM Trans. Archit. Code Optim. 2007 |
Methods — techniques the papers use, named apart from their topics
static cost modeling · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | A compiler cost model for speculative parallelizationabstractSpeculative parallelization is a technique that allows code sections that cannot be fully analyzed by the compiler to be aggressively executed in parallel. However, while speculative parallelization can potentially deliver significant speedups, several overheads associated with this technique can limit these speedups in practice. This paper proposes a novel compiler static cost model of speculative multithreaded execution that can be used to predict the resulting performance. This model attempts to predict the expected speedups, or slowdowns, of the candidate speculative sections based on the estimation of the combined runtime effects of various overheads, and taking into account the scheduling restrictions of most speculative execution environments. The model is based on estimating the likely execution duration of threads and considers all the possible permutations of these threads. This model also produces a quantitative estimate of the speedup, which is different from prior heuristics that only qualitatively estimate the benefits of speculative multithreaded execution. In previous work, a limited version of the framework was evaluated on a number of loops from a collection of SPEC benchmarks that suffer mainly from load imbalance and thread dispatch and commit overheads. In this work, an extended framework is also evaluated on loops that may suffer from data-dependence violations. Experimental results show that prediction accuracy is lower when loops with violations are included. Nevertheless, accuracy is still very high for a static model: the framework can identify, on average, 45% of the loops that cause slowdowns and, on average, 96% of the loops that lead to speedups; it predicts the speedups or slowdowns with an error of less than 20% for an average of 28% of the loops across the benchmarks and with an error of less than 50% for an average of 80% of the loops. Overall, the framework often outperforms, by as much as 25%, a naive approach that attempts to speculatively parallelize all the loops considered, and is able to curb the large slowdowns caused in many cases by this naive approach. Jialin Dou, Marcelo H. Cintra |
ACM Trans. Archit. Code Optim. | 1 |