Demo Data from EDBT 2026 / reviewers in the wild / expert
Ting-Hai Chao
dblp:61/3858
· DBLP profile ↗
4ranked-venue papers
3as first author
0since 2021 · last 1994
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 100% | |
| Theoretical computer science
1 paper |
Graph algorithms and graph theory · 100% |
Topics — the 10 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 3 | 1994 | Rectilinear Steiner tree construction by local and global refinement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 Zero Skew Clock Net Routing · DAC 1992 Combining Logic Minimization and Folding for PLA's · IEEE Trans. Computers 1991 |
Electronic design automation › physical design
routing |
0.0 | 1 | 1994 | Rectilinear Steiner tree construction by local and global refinement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 |
Electronic design automation › physical design › routing
steiner tree construction |
0.0 | 1 | 1994 | Rectilinear Steiner tree construction by local and global refinement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 |
Electronic design automation › physical design
clock routing |
0.0 | 1 | 1992 | Zero Skew Clock Net Routing · DAC 1992 |
Electronic design automation › physical design › clock routing
zero-skew clock routing |
0.0 | 1 | 1992 | Zero Skew Clock Net Routing · DAC 1992 |
Electronic design automation › logic synthesis
logic minimization |
0.0 | 1 | 1991 | Combining Logic Minimization and Folding for PLA's · IEEE Trans. Computers 1991 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1991 | Combining Logic Minimization and Folding for PLA's · IEEE Trans. Computers 1991 |
Electronic design automation › logic synthesis › logic optimization
PLA folding |
0.0 | 1 | 1991 | Combining Logic Minimization and Folding for PLA's · IEEE Trans. Computers 1991 |
Graph algorithms and graph theory
graph algorithms |
0.0 | 1 | 1994 | Rectilinear Steiner tree construction by local and global refinement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 |
Graph algorithms and graph theory › spanning tree
minimum spanning tree |
0.0 | 1 | 1994 | Rectilinear Steiner tree construction by local and global refinement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 |
Methods — techniques the papers use, named apart from their topics
loop detection · 0.0local refinement · 0.0global refinement · 0.0product-term substitution · 0.0network partitioning · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1994 | Rectilinear Steiner tree construction by local and global refinementabstractPresents a new algorithm for constructing a rectilinear Steiner tree (RST) for a given set of points. Starting from a rectilinear minimum spanning tree (MST), the algorithm works by incrementally introducing "good" Steiner points into the point set and generating an MST from the enlarged point set. Steiner points are introduced in two stages according to their essentiality and cost. In the first stage, they are generated from the local structure of the tree; in the second stage, they are generated from the global structure using a loop detection method. The proposed algorithm outperforms most other algorithms of its class by the fact that the average cost improvement over the rectilinear minimum spanning tree is 10.4%, and its time complexity is O(n/sup 2/ log n).> Ting-Hai Chao, Yu-Chin Hsu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1992 | Zero Skew Clock Net Routing
Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho |
DAC | 1 |
| 1991 | Combining Logic Minimization and Folding for PLA'sabstractThe authors present an approach that combines logic minimization and folding for a programmable logic array (PLA). An efficient algorithm is proposed for optimal bipartite column folding. In the algorithm, the authors model the PLA personality matrix as a network and the bipartite PLA folding as a partitioning problem of that network. This folding algorithm is able to find optimal solutions for the benchmarks from the literature. The algorithm also substitutes product terms by their alternatives in order to find the one best suited for folding. The authors combine this algorithm and a logic minimization algorithm into a folding system. When comparing the results to those by a conventional approach, about one half of the benchmarks show area gain if product-term-alternatives exist.> Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao |
IEEE Trans. Computers | 4 |
| 1990 | Rectilinear Steiner Tree Construction by Local and Global RefinementabstractA novel algorithm is presented for constructing a rectilinear Steiner tree (RST) of a given set of points. The algorithm works by incrementally introducing Steiner points from a rectilinear minimum spanning tree (MST) and generating a refined Steiner tree. Steiner points are introduced in two stages according to their importance and cost. In the first stage, they are generated from the local structure of the tree; in the second stage, they are generated from the global structure using a loop detection method. The proposed algorithm outperforms most other algorithms; the average cost improvement over the rectilinear minimum spanning tree is 10.6% and its time complexity is O(n/sup 2/ log n).> Ting-Hai Chao, Yu-Chin Hsu |
ICCAD | 1 |