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Issam B. S. Tlili

dblp:61/4010 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
memory testing
0.012003
A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories · IEEE Trans. Computers 2003
Electronic design automation › hardware verification and test
fault modeling
0.012003
A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories · IEEE Trans. Computers 2003

Methods — techniques the papers use, named apart from their topics

integer linear programming · 0.0
YearPublicationVenuePosition
2003 A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories
abstract
Most memory test algorithms are optimized for a particular memory technology and a particular set of fault models, under the assumption that the memory is bit-oriented, i.e., read and write operations affect only a single bit in the memory. Traditionally, word-oriented memories have been tested by repeated application of a test for bit-oriented memories, whereby a different data background is used during each application. This results in time inefficiencies and limited fault coverage. A systematic way of converting tests for bit-oriented memories into tests for word-oriented memories is presented, distinguishing between interword and intraword faults. The conversion consists of concatenating to the test for interword faults, a test for intraword faults. This approach results in more efficient tests with complete coverage of the targeted faults. Word-oriented memory tests are very important, because most memories have an external data path which is wider than one bit.
Ad J. van de Goor, Issam B. S. Tlili
IEEE Trans. Computers2
1998 March Tests for Word-Oriented Memories
abstract
Most memory test algorithms are optimized tests for a particular memory technology, and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e., read and write operations affect only a single bit in the memory. Traditionally, word-oriented memories have been tested by repeated application of a test for bit-oriented memories whereby a different data background (which depends on the used intra-word fault model) is used during each iteration. This results in rime inefficiencies and limited fault coverage. A new approach for testing word-oriented memories is presented, distinguishing between inter-word and intra-word faults and allowing for a systematic way of converting tests for bit-oriented memories to rests for word-oriented memories. The conversion consists of concatenating the bit-oriented test for inter-word faults with a test for intra-word faults. This approach results in more efficient tests with complete coverage of the targeted faults. Because most memories have an external data path which is wider than one bit, word-oriented memory tests are very important.
Ad J. van de Goor, Issam B. S. Tlili
DATE2
1997 Disturb Neighborhood Pattern Sensitive Fault
abstract
With the increase in memory density, neighborhood pattern sensitive faults (NPSFs) are not only an important fault model for DRAMs but will also become so for SRAMs. NPSFs can be considered generalized versions of simple-cell faults and two-cell coupling faults, whereby the extra cells involved in the NPSF are required to have an enabling value. A new coupling fault model, the disturb fault (CFdst) has been published (van de Goor 1996). It has the property that it is more consistent with the true behavior of the memory, while tests for CFdsts can be designed such that they also cover idempotent CFs. It is the purpose of this paper to extend the concept of CFdsts to NPSFs based on CFdsts (i.e. the Disturb NPSFs) and present tests for those DNPSFs. It will be shown that the tests for DNPSFs are more efficient than those of the traditional tests for NPSFs while they also cover the faults of the traditional NPSFs.
Ad J. van de Goor, Issam B. S. Tlili
VTS2