Mobile phones have become a necessity of modern life and are used for various tasks, including audio calls, text messaging, Web surfing, video streaming, gaming, and payments. Most of these tasks consume significant battery power, which makes public charging services increasingly important. Therefore, there are many public places and private stores have started to provide free charging services. However, there are several issues that restrict the popularity of public charging service. First, people cannot easily find charging spots. Second, there is no effective way to monitor charging status and manage the chargers. Third, a free charging service increases business expenses. To address these issues, we developed a Internet of Things (IoT)-based wireless charging service system, which is called AnyCharge. There are five major components of AnyCharge: 1) a Wi-Fi enabled wireless charger; 2) an IoT gateway; 3) a cloud-based management platform; 4) a secure Wi-Fi auto-connection algorithm; and 5) a mobile app. The charger is connected to an IoT gateway through Wi-Fi using our secure auto-connection algorithm, and the gateways are linked to the cloud server using message queue telemetry transport. The administrators can monitor and control chargers using the management platform. In addition, Android and iOS apps have been created to allow users to locate free chargers and find the shortest route to the nearest charging spot. We initiated a large-scale experimental deployment in Taiwan, Thailand, Singapore, and Japan. More than 200 chargers have been installed in different places, including restaurants, hospitals, telecom stores, and hotels. Statistics shows that there is a strong demand for public charging services.

This paper proposes a novel approach to implement software object in hardware. Data-Memory mapping schemes are investigated and four hardware object design schemes are proposed and implemented on a CAD tool. Performance evaluation is carried out in Altera Ouartus tool in terms of speed, logic elements and number of transitions. The result of experiments shows that object-reference scheme is much better than the other 3 schemes in terms of hardware cost, energy consumption and speed for FPGA implementation.

This paper presents a methodology to transfer self-timed circuit specifications into sequential quantum Boolean circuits (SQBCs) and composable SQBCs (CQBCs). State graphs (SGs) are used to describe the behaviors of self-timed circuits and then are translated into SQBCs based on Toffoli gates. The concept of IP (intellectual property) reuse is applied to the constructed SQBCs to produce reusable and composable quantum Boolean circuits (CQBCs). Therefore, these reusable CQBCs as basic modular components can be exploited to construct more complicated quantum Boolean circuits. A set of self-timed components is successfully and automatically synthesized into CQBCs by our methodology. These CQBCs can be used as building blocks to compose control-path components of self-timed systems.

A lot of papers have been written on error correcting/detecting codes for data transmission, but none of the codes are designed to address error correction for delay-insensitive or semi-delay-insensitive (SDI) data transmission. In this paper we address the problem of SDI communication where errors may occur during transmission or encoding. Three error models for SDI data transmission are defined and the general solution schemes for these models are proposed. An efficient systematic SDI error-correcting code for the four-phase handshaking protocol is designed to solve one asymmetric error model. Our code is efficient in terms of encoding, decoding and completion checking. The novelty of our SDI error-correcting code is that our code can correct errors and detect completion at the same time in SDI data transmission. The proposed schemes are particularly suitable for deep-submicron and high-speed board design.

Integer addition is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a self-timed carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of n. To the best of our knowledge, our adder has the best area-time efficiency which is /spl Theta/(nloglogn). An economic implementation of this adder in CMOS technology is also presented. SPICE simulation results show that, based on random inputs, our 32-bit self-timed carry-lookahead adder is 2.39 and 1.42 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively, and, based on statistical data gathered from a 32-bit ARM simulator, it is 1.99 and 1.83 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively.

To achieve the goal of designing high performance self-timed circuits, one of the key factors is to design a fast completion detection circuit, detecting the completion of the self-timed circuit. Some recent work proposed by Wuu and Yun on completion detection circuits is reviewed. A new design of high performance completion detection circuits for dual-rail self-timed circuits is presented. The results of our SPICE simulation show that our computation-completion detection circuit is more than 9 times faster than Wuu's and Yun's, and our reset-completion detection circuits is 2.7 times faster than Wuu's.

Speed, cost and correctness may be the most important factors in designing a digital system. This paper proposes a novel and general methodology to synthesize iterative functions into potentially high speed low cost and very robust circuits, called delay-insensitive combinational tree iterative circuits. In particular our methodology can be applied to synthesize binary addition and comparison into delay insensitive adders and comparators.

In this paper, we present methods for synthesizing multilevel asynchronous circuits to be both hazard free and completely testable. Making an asynchronous two-level circuit hazard free usually requires the introduction of either redundant or nonprime cubes or both. This adversely affects the circuit's testability. However, using extra inputs, which is seldom necessary, and a synthesis-for-testability method, we convert the two-level circuit into a multilevel circuit that is completely testable. To avoid the addition of extra inputs as much as possible, we introduce new exact minimization algorithms for hazard-free two-level logic where we first minimize the number of redundant cubes and then minimize the number of nonprime cubes. We target both the stuck-at and robust path delay fault models using similar methods. However, the area overhead for the latter may be slightly higher than for the former.