A crosstalk compensation (XTC) receiver is proposed for a single-ended four-level pulse amplitude modulation (PAM-4) signaling DRAM interface. The receiver compensates for the crosstalk from two adjacent pin signals by using an RC circuit per pin. The transmitter of the test chip consists of a voltage-mode PAM-4 driver and a three-tap feed-forward equalizer. The XTC circuit at the test chip receiver consists of six blocks of a current-integrating differential amplifier per pin. The current integrating differential amplifier includes three differential pairs, one for its own pin data and the other two for adjacent pin data. The test chip, fabricated on a 28-nm CMOS low-power process, worked successfully at a data rate of 24 Gb/s per pin with four parallel 5-cm long microstrip lines on an FR-4 printed circuit board. The width was 14-mil and the center-to-center spacing was 35-mil. Compared to the previous crosstalk compensation scheme that uses three or more multi-pins, each with one RC circuit and two CR circuits per pin, the transmission coefficient at the receiver input pin was enhanced by 1.31 dB from –1.89 dB to –0.58 dB at the Nyquist frequency of 6 GHz. The XTC circuit opened the closed eyes of both the second and the third pin data among the four data pins of the test chip to 0.12 UI at 24 Gb/s per pin with PAM-4 signaling and bit error rate of 10$^{-12}$. The energy efficiency of the receiver test chip was 1.28 pJ/bit at the 1.1 V supply.

Pitch mark (PM) is a time point corresponding to the closing time of vocal fold in voiced speech. PMs are useful for real-life speech processing because of their noise immunity. Wave-U-PM, a Wave-U-Net based neural network, is proposed to detect PMs from noisy speech. The ground truth PMs are generated from clean speech by using REAPER; this increases the available speech dataset for training to 100 hours, while the dataset for the electroglottograph (EGG) based PM detection is less than 5 hours. Wave-U-PM has an encoder and two decoders. The first decoder generates a sinusoidal PM waveform, whose positive peak times represent the PMs. The second decoder generates a combined pitch and formant waveform below 1000Hz. Wave-U-PM outperforms previous PM detection works by 11% and 31% for the voiced and the entire speech intervals, respectively, in the identification rate (IDR) at 0 dB SNR. The second decoder enhances IDR by 2.5% for the entire speech interval.

We present the first FFE SST TX layout generator enhanced by various software techniques including a GUI-based template engine. Seven different DRC/LVS-clean TXs were generated in multiple technologies (40nm/65nm/90nm CMOS) for the first time, and achieved adequate maximum data rates: 36Gb/s with 40nm in post-layout simulation; 14Gb/s with 65nm in measurement. Total generation time was less than 5 days, including iterative parameter tuning by a human designer and computation (30 minutes for TX core, 8 hours for power network). Fast post-layout analysis of TX’s performance-power trade-off was enabled by the presented generator for the first time.

For the first time, we prove that 7.8-Gb/s single-ended signaling through a highly reflective channel is feasible at low energy cost by an energy-efficient many-tap decision feedback equalization (DFE) receiver (RX). The reported data rate of 7.8 Gb/s is the fastest data rate that has been achieved through a single-ended highly reflective channel that has more than five taps of postcursor reflective intersymbol interference. Compared with the prior arts, the target multidrop has the most in-band notches: ten notches. To compensate for large reflection by many notches, the RX exploits the DFE with the largest tap count of 20 that has been never used in single-ended signaling before. Low-power circuit techniques such as a current-integrating summer and double-tail sense amplifiers were adequately adopted and engineered to reduce large power dissipation by many taps. The RX was fabricated in a 65-nm CMOS technology and occupies only 0.014 mm2. The energy efficiency was measured to be only 2.9 pJ/b at 7.8 Gb/s with 0.9-V supply, proving that fast single-ended signaling through a highly reflective channel is feasible at low energy cost by many-tap DFE if low-power circuit techniques are adequately applied. The horizontal and vertical eye sizes were measured to be 0.12 UI and 34 mV, respectively, at a bit error rate of-12.

This paper presents a sub-10 nW bandgap reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit was implemented with a 0.18μm CMOS process and generates voltage and current references of 1.238 V and 6.64 nA while consuming 9.3 nW. The voltage and current references show standard deviations of 0.43 % and 1.19 % with temperature coefficients of 26 ppm/°C and 283 ppm/°C, respectively.

This paper presents a body-channel communication (BCC) transceiver adopted with decision feedback equalization (DFE). The proposed transceiver, fabricated in 65-nm CMOS process, achieves reliable (BER-6) data rates of 150 Mb/s (16.6 pJ/b), and 100 Mb/s (23.5 pJ/b) over 20-cm and 1.3-m channels on human limbs. The transceiver occupies a total core area of 5580 qm2, which is less than 1% compared to any previously-presented work.

This paper presents an amplifier-less and digital-intensive current-to-digital converter for biosensors. The proposed circuit achieves a first-order noise shaping of the quantization error without any continuous-time feedback circuit. Also, it minimizes static power consumption by employing a single-ended current-steering digital-to-analog converter (DAC) which flows only the same current as the input. The effect of dynamic switching noise become input-independent constant by adopting switching averaging algorithm. The implemented circuit in 0.35pm CMOS converts an input range of 2.8pA to 15b digital output in about 4ms, while consuming 16.8pW.

In this paper, we propose a search algorithm to find the worst operation scenario of a cross-point array of a phase-change random access memory to enable a precise read margin evaluation. The search algorithm utilizes a particle swarm optimization method to find the worst scenario quickly and efficiently. In an experiment, the proposed algorithm improves the search speed by 39.3× compared with the previous algorithm. With the improved search speed, the proposed algorithm could find the worst operation scenarios of large arrays whose worst operation scenarios had been only guessed before. In the experiment with a large array, the proposed algorithm proved that the worst high-resistance state read current can be 36× larger than the previous best guess. In the reliability test, the evaluation error of the worst read current found by the proposed algorithm is less than 0.2% with 99% probability. These results show that the proposed search algorithm can improve the precision and efficiency of the read margin evaluation in designing a cross-point phase-change memory array.

An all-synthesizable current-mode transmitter driver for a USB2.0 high-speed (480 Mb/s) interface was proposed to enhance the design portability. The proposed driver was implemented using tristate inverter cells. It uses the differential current-mode architecture, with variable output voltage swing, and includes a predriver. It was also successfully applied to the 480-Mb/s USB2.0 TX driver with the synthesized serializer and phase-locked loop.

This paper disproves the worst read scenario of a ReRAM crossbar array. If the previously believed worst read scenario is not the worst one, the read margin evaluated based on the scenario can be incorrect. We explored for read scenario worse than the previously believed worst scenario by wisely sampling scenarios and iteratively searching for the worse one. In experiment, our algorithm successfully found the scenario worse than the previously believed one, disproving the previously believed worst read scenario. Our results show that the sensing window estimated by the incorrect previously believed worst scenario is 14 times as large as the estimation by the worst scenario found by our algorithm.

This paper proposes a technique to reduce the sample number of channel's pulse response required to optimize equalization coefficients. In our method, channel's pulse response is aliased in calculating equalization coefficients reducing the number of samples of the channel's frequency response. As a result, the computation time to acquire the channel's frequency response is greatly reduced. To demonstrate our method, equalization coefficients are calculated using the conventional and our methods and then compared. Since the necessary number of samples is reduced by 8 times at most in our method, the computation time is reduced up to by 7.01 times. For accuracy verification, we also calculated the equalized eye sizes using both methods. The calculated eye sizes are almost identical. These results show that using our method, engineers can accurately optimize equalizing transceiver design with reduced efforts to simulate channel's frequency response.

The time-periodic property of the LCD VCOM noise is utilized to reduce the effect of the VCOM noise on the mutual-capacitance measuring touch sensor placed on a LCD panel. The amplitude of the touch sensor driving signal (VSTM) can be reduced reliably down to 0.4 V with the reporting rate of 189 Hz, by using the following two methods. (1) The frequency of VSTM is set to (n+0.5)·fN, by synchronizing VSTM to a LCD gate driver signal with a referenceless CDR. fN is the inverse of the LCD VCOM noise period (TN) and n is a positive integer. (2) The reset period of the RX integrator is set to 2·TN.

A new empirical model for the threshold voltage of enhancement NMOSFET is proposed based on experimental observations. This model covers both short and narrow channel effects. The model equation is formulated by the superposition of these two effects, and extraction of model parameters is presented. Comparison of the model with experimentally measured values shows good agreement for transistors with effective channel length down to 1.8 μm and effective channel width down to 1.0 μm.