Methodology which incorporates the philosophy and methods of Taguchi is developed to address the issues of designing for manufacturability and sensitivity analysis. Specifically, the goal is to obtain responses (outputs) at or near required targets and to minimize output variability when the inputs are subject to manufacturing tolerances. The desirability functions, which generalize the notion of yield, are used to assess how close responses are to their targets. Manufacturing tolerances in the inputs are incorporated in the analysis by means of the expected loss of the desirability function which is estimated by a Taguchi outer array approach. The desirability expected loss is used to determine an optimum nominal input point to give responses close to target with small variability. The sensitivity of the various responses to the inputs is determined by an analytical method and an analysis of variance approach using a Taguchi outer array. The methods are applied to the optimization of a BIMOS NPN transistor.>

A statistically oriented methodology for optimization and sensitivity analysis of VLSI process, device, and circuit design through computer simulation has been developed. Emphasis has been placed on maintaining a clear distinction between design synthesis and design analysis. Design analysis is viewed as a multiple input-output system resulting in a multiple-constraints-optimization problem. It is shown how simple graphic techniques or rigorous mathematical optimization can be performed within a constrained desirability space to determine optimal operating conditions. This leads directly to the concept of global input factors. Which affect a large number of the response variables, and specific input factors, which can be used to adjust the operating level of a small number of response variables. By using the derived empirical equations to desensitize the responses to variations in input factors, the proposed methodology can play a key role in designing for manufacturability. As proof of concept, the methodology has been applied to the optimization of a VLSI BIMOS technology, with satisfactory results.>