Demo Data from EDBT 2026 / reviewers in the wild / expert
Chia-Kai Yang
dblp:61/5629
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2008
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 1 | 2003 | Test pattern generation and clock disabling for simultaneous test time and power reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Electronic design automation › hardware verification and test › design for testability
scan-based testing |
0.0 | 1 | 2003 | Test pattern generation and clock disabling for simultaneous test time and power reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Electronic design automation › hardware verification and test
test application time reduction |
0.0 | 1 | 2003 | Test pattern generation and clock disabling for simultaneous test time and power reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 2003 | Test pattern generation and clock disabling for simultaneous test time and power reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Electronic design automation › hardware verification and test › low-power testing
test power reduction |
0.0 | 1 | 2003 | Test pattern generation and clock disabling for simultaneous test time and power reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Methods — techniques the papers use, named apart from their topics
scan architecture modification · 0.0multiple clock disabling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2008 | Characterizing the Meso-Scale Enviromental Thermal Effects Due to Different Landuse Types using Remote Sensing Techniques and Indices in Taoyuan, North TaiwanabstractThe purpose of this paper was to characterize the mesoscale environmental thermal effects due to different landuse types in Taoyuan, north Taiwan with the application of remote sensing techniques and indices. A LandSat 7 ETM+ image was utilized to characterize the spatial distribution of land surface temperature and the average temperatures of different land use types. Two remote sensing indices, Normalized Difference Vegetation Index (NDVI) and Normalized Difference Moisture Index (NDMI) were calculated in each pixel of the image and linearly regressed with the surface temperature. The results showed that the average land surface temperatures in urban area and bare land was 3.43degC and 2.58degC higher and those in grassland, forest, waterbody, and rice paddies was 0.78degC, 0.70degC, 2.79degC, and 2.87 degC lower than the overall average temperature. It was also found that the surface temperature reduced 1.3degC for every increment of 0.1 in the NDVI and reduced 1.7degC for that in the NDMI. It demonstrated that surface moisture content and vegetation coverage greatly influenced land surface temperature. Chia-Kai Yang, Chih-Hung Tan, Chung-Hsin Juan, Meng-Lung Lin |
IGARSS (3) | 1 |
| 2003 | Test pattern generation and clock disabling for simultaneous test time and power reductionabstractScan-based design has been widely used to transport test patterns in a system-on-a-chip (SOC) test architecture. Two problems that are becoming quite critical for scan-based testing are long test application time and high test power consumption. Previously, many efficient methods have been developed to address these two problems separately. In this paper, we propose a novel method called the multiple clock disabling (MCD) technique to reduce test application time and test power dissipation simultaneously. Our method is made possible by cleverly modifying and integrating a number of existing techniques to generate a special set of test patterns that is suitable for a scan architecture based on the MCD technique. Experimental results for the International Symposium on Circuits and Systems (ISCAS) '85 and '89 benchmark circuits show that significant reduction on both test application time and power dissipation can be achieved compared to the conventional scan method. Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |