Simulation models of a variety of computer architectures have been created using HASE, a Hierarchical Computer Architecture design and Simulation Environment. Some of these models were previously available as applets but using the models directly in a new version of HASE, itself now available for downloading, has proved more satisfactory.

The conference on grand challenges, held in Newcastle on 30 and 31 March 2004, occurred at a particularly opportune time. The strand on the educational aspects was particularly relevant and the idea innovative in the sense that this was the first occasion on which a grand challenge event with a focus on educational issues in computing had taken place. This paper provides some of the background and includes a distillation of the educational challenges that emerged from that event.

Simulation models of a number of computer architectures have been created using HASE,a Hierarchical Computer Architecture design and Simulation Environment,and automatially translated into WebHASE... and JavaHASE applets which can be accessed via the WWW.These applets are being used both as visual aids and or student exercises.

The operation of a computer can be conceptualised as a large, discrete and constantly changing set of state information. However even for the simplest uni-processor the data set of such a model is very large and is subject to rapid change. We show how HASE provides an interactive animated display of a given computer system’s components allowing visualisation of the data set (and consequently the mechanisms employed by computer architects when designing a computer system). Simulation models of both the DLX and DASH architectures are discussed, demonstrating HASE’s suitability as a teaching tool for computer architecture students. 1. The Problem In trying to understand the detailed operation of a computer, the computer science student must consider the constantly changing state of its individual components. One natural way to represent this state information is by means of a set of diagrams. However even for the simplest uni-processor the set of data to be conveyed by such means is very large (memory contents, cache contents and registers for example) and is subject to rapid change. This presents the scientist with a problem- how to represent a large, ever changing set of state information with a sufficiently fine time resolution to be useful. Given these requirements it is natural to look for some form of tool to help with this data management job. 2. HASE

HASE is a Hierarchical computer Architecture design and Simulation Environment (HASE) which allows for the rapid development and exploration of computer architectures at multiple levels of abstraction, encompassing both hardware and software. The components of a computer system lend themselves naturally to being modelled as objects, so HASE has been implemented in an object-oriented language. Within HASE there are graphical entity design and edit facilities, entity library creation and retrieval mechanisms, an animator, and statistical analysis and experimentation tools for deriving system performance metrics. HASE uses an object-oriented database management system (ObjectStore) to make the design objects and the entity library persistent. For each architecture model HASE allows many experiments with varying parameters to be performed. The database facilities provided through HASE manage not only the results of each experiment, but also their relationship to the state of the architecture model that produced these results, including all input and output parameters and their values during the experiment. This paper describes the design of HASE, some of the varied projects which have used it, and the future direction of the system.

We discuss the algorithmic steps involved in common sparse matrix problems, with particular emphasis on linear programming by the revised simplex method. We then propose new architectural mechanisms which are being built into an experimental machine, the Edinburgh Sparse Processor, and which enable vector instructions to operate efficiently on sparse vectors stored in compressed form. Finally, we review the use of these new mechanisms on the linear programming problem.

MU6V is a parallel vector processing system in which a linear set of processors, each capable of both vector and scalar operations, is interconnected by a common communication highway.Memory is fully distributed among the processors and interprocessor communication occurs by means of global broadcasts controlled in hardware by a data driven synchronization mechanism.A prototype model based on 68000 microprocessors, in which vector orders are emulated as "extracodes", has been constructed.A host machine provides a software support environment and a run-time system in the prototype provides diagnostic information.Programming language features have been designed to exploit this configuration and an example algorithm is presented.

The performance of pipelined processors is heavily influenced by the effects of control-transfer, or branching, instructions, and various strategies have been used to reduce the delays incurred by these instructions. The position of the "control point" in the pipeline is an important factor that must also be taken into account, however, and this paper presents an analysis of its effects. Results are given of measurements made with a hardware performance monitor during the running of benchmark programs on the highly pipelined MU5 processor. These results support the argument for placing the control point as late in the pipeline as possible, and for using a prediction mechanism to supply correct sequences of instructions to the pipeline.

One of the most important concepts in MU5 is the use of a Name Store to hold the small number of frequently used named variables found in high level language programs. This paper describes the implementation of this store as part of the MU5 processor and presents some results of measurements of its performance.

MU5 is a high speed general purpose computer designed to meet the requirements of high level languages. The order code is such that several distinct operations are involved in accessing an operand. Operands specified directly by instructions are accessed by the instruction processing unit described in this paper. This unit is designed as a pipeline in which several instructions are in different stages of processing at any one time. A significant improvement in performance is obtained by this technique although detailed requirements of the order code deteriorate the performance in practice. An assessment of the expected overall performance is given.