A new methodology is used for the design verification of bipolar array chips. Here the authors apply analog methods to verify the logic function of the chip's basic circuits or macromodels and the noise margins. They also check for reliability by computing the current density at each device contact stud. The logic paths are implicitly verified. Several algorithms are used as building blocks in an implementation program. This includes a recursive scheduling algorithm, a Gray algorithm and an algorithm to treat differential pairs. A nonlinear Gauss-Seidel method for decoupling and solving a nonlinear set of algebraic equations is described.>

HLSIM is an APL hierarchical logic simulator that can deal with nested models. The program has all the facilities to handle large VLSI circuits with complicated sequential logic, including full chip simulation. The authors discuss two major programs: an analog to digital netlist converter and a new digital simulator implemented in APL, a natural environment for logic simulators, especially when its powerful APL nested array facilities are used. The netlist converter takes a hierarchical analog netlist and supplementary files for the leaf models, and creates a digital model of the VLSI circuit. A discussion of the simulator includes its data structure, two algorithms for the static (zero) and the dynamic (unit or variable) delay modes of simulation. The authors also discuss how to handle unique features of the bipolar circuits including emitter, collector dots and differential pairs. Three types of gates can be used: primitive, truth tables, and behavioral models implemented as arbitrary user functions. The last feature enabled them to model and simulate complicated bipolar chips and decoders.>