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EDBT 2026 Demo / reviewers in the wild / expert

Jorge E. Carrillo

dblp:61/5965 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2001
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 67% Processor architecture and microarchitecture · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › reconfigurable architecture
reconfigurable functional unit		 0.012001
The effect of reconfigurable units in superscalar processors · FPGA 2001
Reconfigurable computing and FPGAs › reconfigurable architecture
reconfigurable processor		 0.012001
The effect of reconfigurable units in superscalar processors · FPGA 2001
Processor architecture and microarchitecture
superscalar processor		 0.012001
The effect of reconfigurable units in superscalar processors · FPGA 2001

Methods — techniques the papers use, named apart from their topics

dynamic scheduling · 0.0dynamic reconfiguration · 0.0LRU configuration management · 0.0
YearPublicationVenuePosition
2001 The effect of reconfigurable units in superscalar processors
abstract
This paper describes OneChip, a third generation reconfigurable processor architecture that integrates a Reconfigurable Functional Unit (RFU) into a superscalar Reduced Instruction Set Computer (RISC) processor's pipeline. The architecture allows dynamic scheduling and dynamic reconfiguration. It also provides support for pre-loading configurations and for Least Recently Used (LRU) configuration management.
Jorge E. Carrillo, Paul Chow
 FPGA1