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Wai Hong Ho

dblp:61/6085 · DBLP profile ↗
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4ranked-venue papers
4as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Interconnection networks and networks-on-chip · 86% Electronic design automation · 14%
Computer networks
1 paper
Network performance modeling · 100%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip
network topology
0.122003
A clustering approach for identifying and quantifying irregularities in interconnection networks · IEEE Trans. Parallel Distributed Syst. 2003
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns · HPCA 2003
Interconnection networks and networks-on-chip
on-chip interconnect
0.112006
A Design Methodology for Efficient Application-Specific On-Chip Interconnects · IEEE Trans. Parallel Distributed Syst. 2006
Interconnection networks and networks-on-chip › network topology › static interconnection networks
irregular topology
0.012003
A clustering approach for identifying and quantifying irregularities in interconnection networks · IEEE Trans. Parallel Distributed Syst. 2003
Interconnection networks and networks-on-chip
network-on-chip design
0.012003
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns · HPCA 2003
Electronic design automation › physical design
interconnect synthesis
0.012006
A Design Methodology for Efficient Application-Specific On-Chip Interconnects · IEEE Trans. Parallel Distributed Syst. 2006
Electronic design automation
physical design
0.012006
A Design Methodology for Efficient Application-Specific On-Chip Interconnects · IEEE Trans. Parallel Distributed Syst. 2006
Network performance modeling › throughput analysis
saturation throughput
0.012003
A clustering approach for identifying and quantifying irregularities in interconnection networks · IEEE Trans. Parallel Distributed Syst. 2003
Interconnection networks and networks-on-chip › interconnection networks
parallel computer interconnection
0.012003
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns · HPCA 2003

Methods — techniques the papers use, named apart from their topics

simulation · 0.1clustering algorithm · 0.1temporal and spatial model · 0.1recursive bisection · 0.1temporal and spatial communication model · 0.0
YearPublicationVenuePosition
2006 A Design Methodology for Efficient Application-Specific On-Chip Interconnects
abstract
As the level of chip-integration continues to advance at a fast pace, the desire for efficient interconnects - whether on-chip or off-chip - is rapidly increasing. Traditional interconnects like buses, point-to-point wires, and regular topologies may suffer from poor resource sharing in the time and space domains, leading to high contention or low resource utilization. In this paper, we propose a design methodology for constructing networks for special-purpose computer systems with well-behaved (known) communication characteristics. A temporal and spatial model is proposed to define the sufficient condition for contention-free communication. Based upon this model, a design methodology using a recursive bisection technique is applied to systematically partition a parallel system such that the required number of links and switches is minimized while achieving low contention. Results show that the design methodology can generate more optimized on-chip networks with up to 60 percent fewer resources than meshes or tori while providing blocking performance closer to that of a fully connected crossbar.
Wai Hong Ho, Timothy M. Pinkston
IEEE Trans. Parallel Distributed Syst.1
2003 A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
abstract
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects - whether on-chip or off-chip - is rapidly increasing. Traditional interconnects like buses, point-to-point wires and regular topologies may suffer from poor resource sharing in the time and space domains, leading to high contention or low resource utilization. In this paper, we propose a design methodology for constructing networks for special-purpose computer systems with well-behaved (known) communication characteristics. A temporal and spatial model is proposed to define the sufficient condition for contention-free communication. Based upon this model, a design methodology using a recursive bisection technique is applied to systematically partition a parallel system such that the required number of links and switches is minimized while achieving low contention. Results show that the design methodology can generate more optimized on-chip networks with up to 60% fewer resources than meshes or tori while providing blocking performance closer to that of a fully connected crossbar.
Wai Hong Ho, Timothy M. Pinkston
HPCA1
2003 A clustering approach for identifying and quantifying irregularities in interconnection networks
abstract
Support for arbitrary topologies has become more popular for system-area networks but very little has been done in trying to characterize their behavior and performance. Traditional parameters like diameter and bisection width are not sufficient for characterizing the irregularities that abound in such networks and fail to give much insight into throughput performance. A clustering approach for partitioning a network into clusters of richly-connected regions is proposed as a means of defining two performance-correlated characterization metrics: intercluster bandwidth index and intercluster link-cost index. The two characterization metrics are shown to have a strong correlation to saturation throughput when link and load distribution of a network is imbalanced. Simulation results also show that the clustering algorithm can be applied to a variety of network configurations and traffic scenarios, particularly irregular ones. With the proposed characterization metrics that correlate more strongly with performance, it is possible to classify networks into categories having similar performance.
Wai Hong Ho, Timothy M. Pinkston
IEEE Trans. Parallel Distributed Syst.1
1998 A clustering approach in characterizing interconnection networks
abstract
Networks of workstations (NOW) have gained importance in recent years. The interconnection network of NOW systems often consist of generic switches connected in an irregular topology. Traditionally, interconnection networks are characterized by their topological properties, such as number of nodes, diameter, and bisection width. These parameters are not sufficient in characterizing irregular networks. This research puts forth a new approach that characterizes both regular and irregular networks. A partitioning algorithm is proposed to break down a network topology into groups or clusters of nodes such that there is higher bandwidth within clusters than between clusters. By doing so, the potential bottlenecks of a network are identified. Furthermore, a characterization scheme based on measurement of these clusters is defined. The new scheme uses two parameters, the intercluster bandwidth index and intercluster link cost index to describe a network topology. Simulation results show that these two indices have stronger correlation to performance than traditional topological properties.
Wai Hong Ho, Timothy M. Pinkston
HiPC1