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EDBT 2026 Demo / reviewers in the wild / expert

Real G. Pomerleau

dblp:61/6115 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › gate sizing
driver sizing		 0.011999
Improved Selay Prediction for On-Chip Buses · DAC 1999
Electronic design automation
physical design		 0.011999
Improved Selay Prediction for On-Chip Buses · DAC 1999

Methods — techniques the papers use, named apart from their topics

elmore delay model · 0.0RC tree analysis · 0.0
YearPublicationVenuePosition
1999 Improved Selay Prediction for On-Chip Buses
abstract
In this paper, we introduce a simple procedure to predict wiring delay in bi-directional buses and a way of properly sizing the driver for each of its port. In addition, we propose a simple calibration procedure to improve its delay prediction over the Elmore delay of the RC tree. The technique is fast, accurate, and ideal for implementation in floorplanner during behavioral synthesis.
Real G. Pomerleau, Paul D. Frazon, Griff L. Bilbro
 DAC1