Demo Data from EDBT 2026 / reviewers in the wild / expert
Gideon D. Intrater
dblp:61/655
· DBLP profile ↗
5ranked-venue papers
4as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 4 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 65% Memory systems · 31% Performance modeling and evaluation · 4% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › instruction fetch
decoded instruction cache |
0.0 | 2 | 1994 | Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers · IEEE Trans. Computers 1994 Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers · ISCA 1992 |
Processor architecture and microarchitecture › pipelining
delayed branch |
0.0 | 2 | 1994 | Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers · IEEE Trans. Computers 1994 Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers · ISCA 1992 |
Memory systems › cache › CPU cache
instruction cache |
0.0 | 2 | 1994 | Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers · IEEE Trans. Computers 1994 Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers · ISCA 1992 |
Processor architecture and microarchitecture › pipelining
instruction pipeline |
0.0 | 1 | 1994 | Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers · IEEE Trans. Computers 1994 |
Memory systems
cache |
0.0 | 1 | 1992 | Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers · ISCA 1992 |
Processor architecture and microarchitecture
pipelining |
0.0 | 1 | 1992 | Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers · ISCA 1992 |
Performance modeling and evaluation
cache performance modeling |
0.0 | 1 | 1994 | Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers · IEEE Trans. Computers 1994 |
Methods — techniques the papers use, named apart from their topics
trace-driven simulation · 0.0analytical modeling · 0.0performance evaluation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | The world's first USB3.0 storage controller
Gideon D. Intrater |
Hot Chips Symposium | 1 |
| 1994 | Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length ComputersabstractA Decoded INstruction Cache (DINC) is a buffer between the instruction decoder and other instruction pipeline stages. In this paper, we explain how techniques that reduce the branch penalty on a DINC, can improve CPU performance. We also analyze the impact of some of the design parameters of DINC's on variable instruction length computers. Our study indicates that tuning the mapping of the instructions into the cache can improve performance substantially. Tuning must be based on the instruction length distribution for a specific architecture. In addition, the associativity degree has a greater effect on the DINC's performance than on the performance of regular caches. We discuss the difference between the performance of DINC's and other caches, when longer cache lines are used. We present a model to estimate the miss rate based on its characteristics, that are discussed and analyzed throughout this paper. Our conclusions are based on both analytical study and trace driven simulations of several integer UNIX applications.> Gideon D. Intrater, Ilan Y. Spillinger |
IEEE Trans. Computers | 1 |
| 1992 | NSC's Digital Answering Machine SolutionabstractA digital signal processing capability that allows data compression and the use of cost effective memories, both fundamental to digital answering machines (DAMs), is reported. It is provided by a three-chip cluster, tuned to the DAM application and based on the NS32AM160. This cluster offers a solution to both the processing power and system integration requirements.> Ohad Falik, Gideon D. Intrater |
ICCD | 2 |
| 1992 | Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length ComputersabstractA Decoded INstruction Cache (DINC) serves as a buffer between the instruction decoder and the other instruction-pipeline stages. In this paper we explain how techniques that reduce the branch penalty based on such a cache, can improve CPU performance. We analyze the impact of some of the design parameters of DINCs on variable instruction-length computers, e.g., CISC machines. Gideon D. Intrater, Ilan Y. Spillinger |
ISCA | 1 |
| 1990 | Application specific microprocessor [NS3200/EP family]abstractAn alternative approach for embedded system processor architecture is presented. Methods to evaluate and define the modules within such a processor are discussed. Three examples of new embedded system processors from the National Semiconductors 32000/EP family are described. These are: the integrated system processor NS32CG160 developed for laser beam printer applications; the embedded system processor NS32GX320 for laser/FAX applications; and the imaging signal processor NS532FX16 designed for Group 3 FAX machines. Integration of system components and improved internal organization should deliver better solutions for the embedded application designer.> Gideon D. Intrater, Dan Biran |
ICCD | 1 |