In recent years, we learned to live with a slow-down in the growth rates predicted so far with remarkable accuracy by Moore's law. However, this does not necessarily mean that advancements in performance and reduced power consumption are not possible anymore. There will be more innovations and improvements in processor and system architecture and microarchitecture than before, which will enable continued growth - at Intel, and in the industry. Intel has identified several areas which deserve focused efforts and investment, with the promise of providing in return growth and results we came to expect. Manufacturing processes constitute the first such area. Besides using more advanced technologies to achieve smaller features on our ICs, Intel is also introducing advanced packaging solutions, which will enable exponential scaling in computing density by extending transistor placement in a third dimension. The second area is that of processor and system architecture. Computing architectures from Intel span most of the existing compute spectrum, with scalar, vector, matrix, and spatial architectures. These map roughly to our CPUs, GPUs, accelerators, and FPGAs.

The Intel®AVX-512 architecture adds new capabilities such as masked execution, floating-point exception suppression and static rounding modes, as well as a small set of new instructions for mathematical library support. These new features allow for better compliance with floating-point or language standards (e.g. no spurious floating-point exceptions, and faster or more accurate code for directed rounding modes), as well as simpler, smaller footprint implementations that eliminate branches and special case paths. Performance is also improved, in particular for vector mathematical functions (which benefit from easier processing in the main path, and fast access to small lookup tables). In this paper, we describe the relevant new features and their possible applications to floating-point computation. The code examples include a few compact implementation sequences for some common vector mathematical functions.

The paper establishes several simple, but useful relationships between ulp (unit in the last place) errors and the corresponding relative errors. These can be used when converting between the two types of errors, ensuring that the least amount of information is lost in the process. The properties presented here were already useful in IEEE conformance proofs for iterative division and square root algorithms, and should be so again to numerical analysts both in 'hand' proofs of error bounds for floating-point computations, and in automated tools which carry out, or support deriving such proofs. In most cases, the properties shown herein establish tighter bounds than found in the literature. They also provide 'conversion' rules of finer granularity, at floating-point value level instead of binade level, and take into account the special conditions which occur at binade ends. For this reason, the paper includes a small, but non-negligible element of novelty.

Exascale level computers might be available in less than a decade. Computer architects are already thinking of, and planning to achieve such levels of performance. It is reasonable to expect that researchers and engineers will carry out scientific and engineering computations more complex than ever before, and will attempt breakthroughs not possible today. If the size of the problems solved on such machines scales accordingly, we may face new issues related to precision, accuracy, performance, and programmability. The paper examines some relevant aspects of this problem.

The special section in this issue focuses on the topic of computer arithmetic.

A brief description is provided of the decimal floating-point support available for IntelregArchitecture processors, compliant with the IEEE Standard 754-2008 for Floating-Point Arithmetic. Some performance results are included.

The IEEE Standard 754-1985 for binary floating-point arithmetic [19] was revised [20], and an important addition is the definition of decimal floating-point arithmetic [8], [24]. This is intended mainly to provide a robust reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. The IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper, which are used in a software implementation of the IEEE 754R decimal floating-point arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms are outlined for the more important or interesting operations of addition, multiplication, and division, including the case of nonhomogeneous operands, as well as conversions between binary and decimal floating-point formats. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations. This paper extends an earlier publication [6].

The IEEE Standard 754-1985 for binary floating-point arithmetic [1] was revised [2], and an important addition is the definition of decimal floating-point arithmetic. This is intended mainly to provide a robust, reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper which are used in a software implementation of the IEEE 754R decimal floatingpoint arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms for the more important or interesting operations of addition, multiplication, division, and conversions between binary and decimal floating-point formats are also outlined. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations.