The advent of Internet of Things (IoT) ushers in a significant potential to integrate individuals, devices, and data, leading to a profound change in our professional and social environments. The small, resource-constrained IoT devices are usually deployed to collect various types of critical data in remote or unmonitored locations. Due to extensive interconnectivity, limited resources, and inadequate security design, IoT systems are vulnerable to communication-specific cyber threats, which aim to disrupt operations, steal sensitive information, or cause damage. To resolve the security concerns in IoT communications, many recent efforts have been devoted to designing authenticated key agreement protocols for IoT systems. However, not only most of the existing solutions fail to adopt cost-effective techniques for resource-limited IoT devices, but also they ignore the differentiation among various data types in the established session keys. A few approaches use traditional physical unclonable functions (PUFs) to address resource concerns, yet they introduce new security issues into IoT systems. Once the PUF cryptographic information is compromised by machine learning attacks, the entire authentication framework collapses. Therefore, in this paper we propose an authenticated key agreement protocol for device-to-gateway communication in IoT systems based on Chebyshev polynomial and probability-based PUF. We examine the proposed protocol’s security features through formal security validation. We also conduct performance evaluation through a simulation-oriented study, and the results clearly prove that the proposed protocol offers superior security and privacy, while maintaining low computational overhead.

This article presents a quantitative study on the performance of an asynchronous chain model [ 31 ] during its theoretical design stage. The asynchronous chain [ 31 ] in this study is asynchronous along with adaptively sized blocks in a proactive manner, whereas the conventional chain controls the block posting in a strictly synchronous manner to the fixed-sized blocks. The model of the adaptive chain, with a rather “reactively” dynamic size of blocks as shown in [ 30 ], can be compared with the proposed model, which is asynchronous with a “proactively” dynamic size of the blocks. It is assumed in this article that Variable Bulk Arrivals (VBA) of transactions in the Poisson distribution and Asynchronous Bulk Posting (ABS) of transactions off a block potentially in different capacity in exponential time, referred to as VBAABS. Basic numerical simulations results have been reported in [ 31 ] primarily for feasibility validation purpose. In our earlier conference version [ 31 ], we have presented the work with the focus on development and validation of the performance model in a quantitative manner with extensive numerical simulations to demonstrate the efficacy of the proposed asynchronous chain model, and in this article, we extend the work to also include substantially new works such as an extensive comparative study in performance versus other blockchain models such as the baseline chain model [ 29 ] (see Comparison between the Asynchronous Chain Model and the Baseline Chain Model) and the adaptive chain model [ 30 ] (see Comparison between the Asynchronous Chain Model and the Adaptive Chain Model under Various Network Traffic). Then, a summary, by each chain model in consideration, is provided for clarity (see Chain Model Insights). Furthermore, a new simulation is conducted with a focus on the performance of microtransactions as a type of transactions to be commonly expected in the gaming decentralized applications to demonstrate the benefit from the proactive asynchrony of block postings (see Simulation and Analysis of the Impact of the Asynchronous Chain Model on the Performance of Microtransactions). Last, the implementation results and analysis are shown based on the Ethereum open source as reported in [ 31 ].

The Internet of Drones (IoD) has latterly started to gear up its applications in diverse sectors of the society as a result of high adaptability and adjustability to new circumstances. Security, privacy, and storage issues still remain as major barriers for next-generation IoD systems to meet their general applicability requirements, even though many one-keyfor-all static authentication and append-only blockchain assisted systems have been proposed by the IoD community. First, bearing channel bandwidth and drones resource constraints in mind, authentication protocols with less computation and communication overhead are preferable. Second, the IoD drones might collect different types of data simultaneously, a unique secret session key for each type of data is needed to prevent data leakage from unauthorized parties. Third, the permanent storage of each drones cryptographic and task information on the appendonly blockchain raises significantly alert after a long period of operation and/or an exponential growth of drones. Motivated by the research challenges presented above, we propose a redactable blockchain-assisted application-aware authentication system, also referred to as ReBAS, for next-generation IoD applications, where the drones shuttle back and forth between different flying zones to collect diverse types of data. The Chebyshev polynomial, redactable consortium blockchain, and chameleon hash function are adopted to significantly minimize the computational, communication, and storage overheads of cryptography-related operations. According to the security verification, and formal and informal security analysis, the ReBAS not only guarantees secure and dynamic authenticated key establishment, but also is in compliance with the security requirements of Canetti-Krawczyk adversarial framework. We also develop a rigorous simulation framework and conduct an extensive comparative study. The experimental results demonstrate that the ReBAS can minimize the overheads in computation, communication, and storage while enhancing scalability.

This research proposes the methodology to extract common configuration parameter set by applying multiple benchmark applications including TeraSort., TestDFSIO, and MrBench on the Hadoop Distributed File System. In the process of determining parameter set for each stage, one parameter and its associated values selected which is reduced system performance in terms of overall execution time difference are measured by multiple applications on a Hadoop cluster. The experimental results demonstrate the proposed extended greedy manner provide a feasible benchmark model for the multiple tasks. In this way, we have found several parameter value sets that can reduce the execution time by 27% of the values provided by Hadoop default.

This paper proposes a method to facilitate the identification process for a set of configuration parameters to achieve the optimal performance with respect to a benchmark program in HDFS in an automated manner. Performance optimization of Hadoop processes is a tedious yet challenging problem due to the complexity of the systems organization with an extensive list of configuration parameters to be considered. An Automated Benchmarking Configuration Method (ABCM) is developed in this work to facilitate the identification process for the set of configuration parameters that minimizes the execution time of a benchmark, namely TestDFSIO Write and Read in particular. A two-phased configuration parameters selection process with a simple sampling technique is proposed in order to mediate the exponential computation time otherwise. By using the proposed technique, we have automatically found the sets of top five selected optimal configuration parameters that reduced the average execution time by 32% compared to the execution time with the default set of Hadoop configuration parameters.

Current implementation of Hadoop is based on an assumption that all the nodes in a Hadoop cluster are homogenous. Data in a Hadoop cluster is split into blocks and are replicated based on the replication factor. Service time for jobs that accesses data stored in Hadoop considerably increases when the number of jobs is greater than the number of copies of data and when the nodes in Hadoop cluster differ much in their processing capabilities. This paper addresses dynamic data rebalancing in a heterogeneous Hadoop cluster. Data rebalancing is done by replicating data dynamically with minimum data movement cost based on the number of incoming parallel mapreduce jobs. Our experiments indicate that as a result of dynamic data rebalancing service time of mapreduce jobs were reduced by over 30% and resource utilization is increased by over 50% when compared against Hadoop.

The six papers in this special section cover a wide spectrum of techniques which are encountered in the design of circuits and systems for nano-scale computing.

We present an approach for fault detection in layered interconnection networks (LINs). An LIN is a generalized multistage interconnection network commonly used in reconfigurable systems; the nets (links) are arranged in sets (referred to as layers) of different size. Switching elements (made of simple switches such as transmission-gate-like devices) are arranged in a cascade to connect pairs of layers. The switching elements of an LIN have the same number of switches, but the switching patterns may not be uniform. A comprehensive fault model for the nets and switches is assumed at physical and behavioral levels. Testing requires configuring the LIN multiple times. Using a graph approach, it is proven that the minimal set of configurations corresponds to the node disjoint path sets. The proposed approach is based on two novel results in the execution of the network flow algorithm to find node disjoint path sets, while retaining optimality in the number of configurations. These objectives are accomplished by finding a feasible flow such that the maximal degree can be iteratively decreased, while guaranteeing the existence of an appropriate circulation. Net adjacencies are also tested for possible bridge faults (shorts). To account for 100 percent fault coverage of bridge faults a postprocessing algorithm may be required; bounds on its complexity are provided. The execution complexity of the proposed approach (inclusive of test vector generation and post-processing) is O(N/sup 4/WL), where N is the total number of nets, W is the number of switches per switching element, and L is the number of layers. Extensive simulation results are provided.

We examine the diagnosis of processor array systems formed as two-dimensional arrays, with boundaries, and either four or eight neighbors for each interior processor. We employ a parallel test schedule. Neighboring processors test each other, and report the results. Our diagnostic objective is to find a fault-free processor or set of processors. The system may then be sequentially diagnosed by repairing those processors tested faulty according to the identified fault-free set, or a job may be run on the identified fault-free processors. We establish an upper bound on the maximum number of faults which can be sustained without invalidating the test results under worst case conditions. We give test schedules and diagnostic algorithms which meet the upper bound as far as the highest order term. We compare these near optimal diagnostic algorithms to alternative algorithms, both new and already in the literature, and against an upper bound ideal case algorithm, which is not necessarily practically realizable. For eight-way array systems with N processors, an ideal algorithm has diagnosability 3N/sup 2/3/-2N/sup 1/2/ plus lower-order terms. No algorithm exists which can exceed this. We give an algorithm which starts with tests on diagonally connected processors, and which achieves approximately this diagnosability. So the given algorithm is optimal to within the two most significant terms of the maximum diagnosability. Similarly, for four-way array systems with N processors, no algorithm can have diagnosability exceeding 3N/sup 2/3//2/sup 1/3/-2N/sup 1/2/ plus lower-order terms. And we give an algorithm which begins with tests arranged in a zigzag pattern, one consisting of pairing nodes for tests in two different directions in two consecutive test stages; this algorithm achieves diagnosability (3/2)(5/2)/sup 1/3/N/sup 2/3/-(5/4)N/sup 1/2/ plus lower-order terms, which is about 0.85 of the upper bound due to an ideal algorithm.

A highly dependable embedded fault-tolerant memory architecture for high performance massively parallel computing applications and its dependability assurance techniques are proposed and discussed in this paper. The proposed fault tolerant memory provides two distinctive repair mechanisms: the permanent laser redundancy reconfiguration during the wafer probe stage in the factory to enhance its manufacturing yield and the dynamic BIST/BISD/BISR (built-in-self-test-diagnosis-repair)-based reconfiguration of the redundant resources in field to maintain high field reliability. The system reliability which is mainly determined by hardware configuration demanded by software and field reconfiguration/repair utilizing unused processor and memory modules is referred to as HW/SW Co-reliability. Various system configuration options in terms of parallel processing unit size and processor/memory intensity are also introduced and their HW/SW Co-reliability characteristics are discussed. A modeling and assurance technique for HW/SW Co-reliability with emphasis on the dependability assurance techniques based on combinatorial modeling suitable for the proposed memory design is developed and validated by extensive parametric simulations. Thereby, design and Implementation of memory-reliability-optimized and highly reliable fault-tolerant field reconfigurable massively parallel computing systems can be achieved.

We address the problem of predicting the yield of a chip composed of cores. A center-satellite model is used to directly represent observed spatial autocorrelation of integrated circuit spot defects. This model is compared to another (large-area clustering) model that only indirectly represents intrawafer correlation. We illustrate that, when different portions of a chip have different susceptibility to defects, the chip layout will affect the predicted yield. This is particularly relevant when portions of a chip are defect-tolerant because their susceptibility to defects is dramatically different. We illustrate how the yield models can be used to predict the utility of making much of a chip (or an embedded core) defect-tolerant. Two yield points parameterized the models. The one extra parameter of, and the suitability of, the center-satellite model allowed it to track the yield data points with less than 1 /10,000 of the error of the large-area clustering model. However, the simpler large-area clustering model is accurate in some circumstances, especially when the chip area is small.

This paper presents an approach for the maximal diagnosis of all faults (stuck-at, open and short) in the interconnect of a random access memory (RAM); and the interconnect includes data and address lines. This approach accomplishes maximal diagnosis under a complex model in which the lines in the interconnect of the RAM can be affected by multiple faults. Maximal diagnosis consists of detection and location of all diagnosable faults as well as type identification of multiple faults affecting each line. The proposed algorithm (referred to as the Improved Maximal Diagnosis Algorithm, or IMDA) requires max{n,m-1}+n+3 WRITE and max{n,m}+2n READ, where n is the number of address lines and m is the number of data lines. IMDA executes in three different steps: the first step diagnoses the data lines (and in particular the stuck-at faults); the second step accomplishes maximal diagnosis of the shorts (involving either the data lines only, or the data and address lines); and the third step completes the diagnosis of the address lines.

This paper investigates the co-effect of hardware and software on the reliability as measured by quality level (or defect level) of configurable multichip module (CMCM) systems. Hardware architecture of CMCM can be configured to accommodate target application design. An application, as provided in a form of software, is partitioned and mapped on the provided configurable hardware. Granularity of an application can be used as a criteria of partitioning and mapping, and can determine the utilization pattern of hardware resources. The utilization pattern of CMCM determines the configuration strategy of available hardware resources based on the application's granularity. Different utilization patterns of an application design on CMCM may result in various impacts on escape tolerance (i.e. the probability to avoid inclusion of hardware resources in the configuration that escaped from testing). A quality level model of CMCM is proposed to capture and trace the co-effect of hardware and software, referred to as co-reliability, with respect to escape-tolerance. Various configuration strategies are proposed and evaluated against various criterion granularity and utilization distributions based on the proposed models and evaluation techniques. Extensive analytical and parametric simulation results are shown.

A stratified technique is proposed for testing multichip module systems. Stratification in multichip modules due to the different nature and procurement of these chips is exploited for achieving a high quality-level at a saving of a significant number of tests during assembly. Unlike conventional random testing, the proposed approach (referred to as the lowest yield-stratum first-testing), takes into account the uneven known-good-yield. In the lowest yield-stratum first-testing approach, the effect of the uneven known-good-yield between strata is analyzed with respect to the variance of known-good-yield and the sample size. The lowest yield-stratum first-testing approach significantly outperforms conventional random testing and random stratified testing. This method is competitive even compared to a conventional exhaustive testing at a very small loss in quality-level by greedy (first) testing the chips in the stratum with lower known-good-yield. A Markov-chain model is developed to analyze these testing approaches under the assumption of physically independent failure of chips in multichip module systems.

In a multiprocessor under normal loading conditions, idle processors offer a natural spare capacity. Previous work attempted to utilize this redundancy to overcome the limitations of classic diagnosability and modular redundancy techniques while providing significant fault tolerance. A common approach is task duplexing. The usefulness of this approach for critical applications, unfortunately, is seriously undermined by its susceptibility to agreement on faulty outcomes (malicious agreement). To assess dependability of duplexing under malicious agreement, we propose a stochastic model which dynamically profiles behavior in the presence of malicious faults. The model uses the so-called policy referred to as NMR on demand (NMROD). Each task in a multiprocessor is duplicated, with additional processors allocated for recovery as needed. NMROD relies on a fault model favoring response correctness over actual fault status, and integrates online repair to provide non-stop operation over an extended period.

This paper presents a new model for analyzing the yield of MCM systems with repair process. It exploits the connectivity of the interconnected chips in which yield degradation due to both neighboring chips and interconnect structure are taken into account. Based on the connectivity, two MCM repair scheduling strategies, Smallest Number of Interconnections First (SNIF) and Smallest Number of Neighboring Chips First (SNCF) are proposed Two other scheduling strategies, Largest Number of Interconnections First (LNIF) and Largest Number of Neighboring Chips First (LNCF) are also introduced and analyzed to further explore the impact of connectivity-based repair scheduling on the overall yield of MCMs. Extensive parametric simulations demonstrate the efficiency of the proposed MCM repair scheduling strategies.

In a multiprocessor under normal loading conditions, idle processors naturally offer spare capacity. Previous work attempted to utilize this redundancy to overcome the limitations of classic diagnosability and modular redundancy techniques while providing significant fault tolerance. A popular approach is task duplexing. The usefulness of this approach for critical applications, unfortunately, is seriously undermined by its susceptibility to agreement on faulty outcomes (malicious agreement). To assess the dependability of duplexing under malicious agreement, we propose a stochastic model which dynamically profiles behavior in the presence of malicious faults. The model uses a more or less typical policy we call NMR on demand (NMROD). Each task in a multiprocessor is duplicated, with additional processors allocated for recovery as needed. NMROD relies on a fault model favoring response correctness over actual fault status, and integrates online repair to provide nonstop operation over an extended period.

This paper presents an efficient algorithm for multi-way balanced partitioning of VLSI circuits. The proposed algorithm is still based on the widely used net-cut model, but its novelty is the potential gain function into the net-cut cost function to relax the single-cell-move constraint (as commonly encountered in the Kernighan-Lin algorithm) for balanced partitioning. This feature permits to move a group of cells (referred to as a Multi-Cell-Move strategy) for partitioning a circuit, while reducing its sensitivity to size constraint. The new multi-way partitioning algorithm is fully analyzed; expressions for the potential gain function (with respect to the multi-move operation) and the cost (for the min-cut objective function) are presented. The time complexity of the proposed partitioning algorithm is O(P/spl times/k/sup 2/ log/sub 2/ (k)), where k is the number of blocks and P is the number of pins. Simulation results are presented and a remarkable improvement is achieved compared with existing algorithms, such as the k-Dual Part algorithm.

This paper presents new algorithms for yield enhancement of redundant memories. These algorithms are based on the technique of spare cutting for a redundant memory chip in which repair is implemented by row/column deletion. Different approaches are proposed: some of these approaches are based on a fully exhaustive process, while others try to heuristically reduce the computational overhead involved in determining the repair-solution.

This paper presents an approach for verifying and validating time-dependent protocols, i.e. protocols for which the time spent for the functions is critical to a successful execution. The proposed approach is a novel modification of the traditional Unique Input/Output (UIO) method by explicitly taking into account the time specification of each edge in a protocol modeled as a finite state machine (FSM). A new FSM model which characterizes the timing properties of the protocol, is proposed. An algorithm which generates a test sequence with minimal traversal time for a time-dependent protocol in polynomial time complexity, is proposed.