Demo Data from EDBT 2026 / reviewers in the wild / expert
Victor Shih
dblp:61/6890
· DBLP profile ↗
5ranked-venue papers
1as first author
0since 2021 · last 2016
0000-0003-2480-185XORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3Human-computer interaction and ubiquitous computing · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 85% Reconfigurable computing and FPGAs · 15% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.2 | 2 | 2008 | Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 FPGA area reduction by multi-output function based sequential resynthesis · DAC 2008 |
Electronic design automation › logic synthesis
boolean matching |
0.1 | 1 | 2008 | Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Electronic design automation › logic synthesis › technology mapping
FPGA technology mapping |
0.1 | 1 | 2008 | Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Electronic design automation › logic synthesis
technology mapping |
0.1 | 1 | 2008 | FPGA area reduction by multi-output function based sequential resynthesis · DAC 2008 |
Electronic design automation
boolean satisfiability |
0.0 | 1 | 2008 | Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 2008 | Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Methods — techniques the papers use, named apart from their topics
symmetry exploitation · 0.1retiming · 0.1incremental SAT · 0.1SAT-based Boolean matching · 0.1SAT solving · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | Closed-loop regulation of user state during a boundary avoidance taskabstractPilot induced oscillations (PIOs) are potentially catastrophic events that occur during flight when pilots attempt to control an aircraft close to a performance or physical boundary. PIO-like behavior is typically observed in boundary avoidance tasks (BAT), which simulate tight performance or physical boundaries and induce high cognitive workload. Our previous research linked the occurrence of PIO-like behavior to network level activity in the brain, where higher states of arousal reduce the flexibility of decision making networks such that less environmental information was incorporated to dynamically adjust action. This led us to hypothesize that down regulating arousal via closed-loop audio feedback of a user state could improve piloting performance by enabling increased decision flexibility. Here we show our initial results testing this hypothesis, where we use a hybrid brain computer interface (hBCI) to dynamically provide feedback to a “pilot” that facilitates their ability to reduce their state of arousal. We conduct a systematic comparison relative to control and sham conditions and test to see if this feedback increases the time a “pilot” can fly before a catastrophic PIO. We find that hBCI feedback, which includes central nervous system components consistent with theta activity in the anterior cingulate cortex (ACC), enables prolonged flight relative to closed-loop control and sham feedback. We also find that this feedback induces changes in pupil diameter which are absent in openloop conditions and closed-loop conditions when feedback is not veridical. Pupil diameter has been reported as a surrogate measure of activity in the locus coeruleus-norepinephrine (LC-NE) system which is also linked to a circuit that includes the ACC. We conclude that the feedback we induce with our hBCI provides preliminary evidence that self-regulation of LC-NE/ACC is possible and can be used to dynamically increase decision flexibility when under high cognitive workload. Josef Faller, Sameer Saproo, Victor Shih, Paul Sajda |
SMC | 3 |
| 2016 | Predicting decision accuracy and certainty in complex brain-machine interactionsabstractA promising application of brain machine interfaces (BMIs) is predicting user cognitive state, particularly in complex and demanding scenarios, so that automation can dynamically and adaptively adjust task parameters to optimize joint human-machine performance. In this paper we analyze neural, physiological and behavioral data recorded during a complex two-person “crew station” task and investigate whether these measures provide information for inferring user decision state. Specifically, we investigate how measures of EEG, pupil dilation, heart rate and response time, can be fused to infer decision confidence and accuracy in two side-tasks occurring throughout a three hour experimental session. One side-task is an auditory task, the other a visual task, both occurring within the context of the crew station scenario (auditory alert and a visual satellite map N-back task). We find that the best prediction performance always fuses EEG and pupil dilation measures, with results yielding between 70%–75% accuracy with respect to whether the subject(s) will skip making the decision (i.e. have high uncertainty) or whether he/she makes an error. Interestingly, the results suggest a possible mechanistic explanation for the utility of the fused measures, specifically the interaction between the locus coeruleus (LC), whose activity is linked to arousal state and can be inferred from pupil dilation, and the anterior cingulate (ACC), which has been linked to decision formation and monitoring and whose activity is typically measured via EEG. In general, our results demonstrate the potential in using fused neuro/physio measures to infer and track human operator decision uncertainty during demanding complex tasks, possibly enabling BMIs to eventually be employed as “cognitive orthotics” for improving man-machine interaction and performance. Victor Shih, Ludan Zhang, Christian Kothe, Scott Makeig, Paul Sajda |
SMC | 1 |
| 2008 | FPGA area reduction by multi-output function based sequential resynthesisabstractWe propose a new resynthesis algorithm for FPGA area reduction. In contrast to existing resynthesis techniques, which consider only single-output Boolean functions and the combinational portion of a circuit, we consider multi-output functions and retiming, and develop effective algorithms that incorporate recent improvements to SAT-based Boolean matching. Our experimental results show that with the optimal logic depth, the resynthesis considering multi-output functions reduces area by up to 0.4% compared to the one considering single-output functions, and the sequential resynthesis reduces area by up to 10% compared to combinational resynthesis when both consider multi-output functions. Furthermore, our proposed resynthesis algorithm reduces area by up to 16% compared to the best existing academic technology mapper, Berkeley ABC. Yu Hu 0002, Victor Shih, Rupak Majumdar, Lei He 0001 |
DAC | 2 |
| 2008 | Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAsabstractBoolean matching is one of the enabling techniques for technology mapping and logic resynthesis of field-programmable gate arrays (FPGAs). Boolean satisfiability (SAT)-based Boolean matching (SAT-BM) has been proposed, but computational complexity prohibits its practical deployment. In this paper, we leverage symmetries present in both Boolean functions and target FPGA architectures to prune the solution space, and we also propose some techniques to reduce the replication runtime for SAT instance generation using the incremental SAT reasoning engine. Experiment shows that our SAT-BM reduces runtime by 226times compared with the original SAT-BM algorithm, making SAT-BM more practical. Yu Hu 0002, Victor Shih, Rupak Majumdar, Lei He 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2007 | Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mappingabstractThe Boolean matching problem is a key procedure in technology mapping for heterogeneous field programmable gate arrays (FPGA), and SAT-based Boolean matching (SAT-BM) provides a highly flexible solution for various FPGA architectures. However, the computational complexity of state-of-the-art SAT-BM prohibits its application practically. In this paper we propose an efficient SAT-BM algorithm by exploring function and architectural symmetries. While the most recent work obtained up to 13times speedup, we achieve up to 200times speedup, when both are compared to the original SAT-BM algorithm. Yu Hu 0002, Victor Shih, Rupak Majumdar, Lei He 0001 |
ICCAD | 2 |