EDBT 2026 Demo / reviewers in the wild / expert
Maneesha Gupta
dblp:61/7269
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10ranked-venue papers
2as first author
5since 2021 · last 2025
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7 · 4 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 1 first-author · 1 since 2021Artificial intelligence and machine learning · 1 · 1 first-author
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | A novel architecture of high performance fully differential two stage RFC OTA designed using DFVF and hybrid cascode compensation techniques
Annu Dabas, Shweta Kumari, Maneesha Gupta, Richa Yadav |
Integr. | 3 |
| 2025 | Design of a new compact multiplier-less memtranstor emulator and its application in neuromorphic and chaos generationabstractThis paper presents a compact configuration of memtranstor (MT), a new memory element having direct relation between magnetic flux (φ) and charge (q). The proposed configuration offers a simple architecture as it is designed without the need of any multiplier or any other complex component. This emulator has been realized by employing one operational transconductance amplifier (OTA), one current differencing transconductance amplifier (CDTA), and one voltage differencing current conveyor (VDCC) along with a few passive components. The emulator captures the fundamental relationship between φ and q, enabling the realization of distinctive pinched hysteresis loops under sinusoidal excitation, a hallmark of memtranstive behavior. It is designed to operate at a supply voltage of ±1.25 V. The circuit offers tunability through the variation in biasing voltages ensuring flexibility for a wide range of applications. The accuracy and dynamic characteristics of the proposed architecture are verified through mathematical analysis and LTSpice simulations with a 180 nm CMOS model. To assess the behavior of the proposed emulator in real environment, process-voltage-temperature analysis has been carried out followed by the designing of full custom layout in an area of 4464.88 μm 2 . Furthermore, non-ideal analysis has been carried out considering the parasitic elements at various terminals of the blocks employed in the circuit design. Additionally, to prove the practical feasibility of the proposed circuit, its operation has been confirmed by macro-models of the designated ICs followed by the bread-board implementation using commercial ICs under ±12 V supply voltage. To demonstrate practical utility, the emulator is employed in two key applications: an artificial synapse for neuromorphic systems and a nonlinear chaotic oscillator, both showcasing its relevance for next-generation memory-driven analog computing. The proposed design stands out due to its low component count, compact design, and ease of integration, making it a promising candidate for emerging fields like neuromorphic engineering and chaos-based systems. Furthermore, it provides valuable insights for future research in MT-based nonlinear dynamics and holds significant potential for advancing MT driven applications in neuromorphic computing and beyond. Manoj Kumar 0032, Shireesh Kumar Rai, Bhawna Aggarwal, Maneesha Gupta |
Integr. | 4 |
| 2023 | Design and analysis of DTMOS based RFC with controlled positive feedback OTA using HSCCM and adaptive biasing technique
Annu Dabas, Shweta Kumari, Maneesha Gupta, Richa Yadav |
Integr. | 3 |
| 2022 | Algorithm to Estimate Scalloping & Banding in Scansar Images and Deep Learning Based Descalloping TechniqueabstractAn algorithm is designed and implemented to estimate the scalloping or banding effects in wide swath ScanSAR images and an Autoencoder based deep learning method is attempted to remove the scalloping from the images which is an independent method and do not use SAR imaging parameters. Various SAR images are analysed to demonstrate the effectiveness of the proposed method. We have used both simulations and the Radar Imaging Satellite (RISAT-1) SAR image for computing the depth of scalloping. The estimation is based using periodic variation (inherent pattern of ScanSAR because of scan mechanism and SAR processing) of Scalloping/Banding noise present in ScanSAR images. The estimated depth of scalloping from the simulated dataset is observed around 4.50 dB & 7.11 dB whereas in RISAT-1 SAR data (uncorrected) acquired over the Amazon Rainforest in HH and HV image is 7.29 dB & 8.42 dB respectively. The deep learning-based technique is proposed to remove scalloping and interscan banding noise from an image, especially SAR images. For developing deep learning-based image denoising solution, large-scale training dataset is required, here we propose scalloping dataset. We had simulated 19,125 images with different scalloping noises for training and testing of our Autoencoder neural network model. We have used many images to evaluate the performance of our neural network model. These include some simulated images and original RISAT-1 image. Experiments on RISAT-1 and simulated images shows good performance of our proposed method which can further be improved utilizing realistic datasets. Neil Saxena, Maneesha Gupta, Jahnavi T. Patel |
IGARSS | 2 |
| 2022 | Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application
Mihika Mahendra, Shweta Kumari, Maneesha Gupta |
Integr. | 3 |
| 2019 | RISAT-1 SAR HRS Mode Data Quality EvaluationabstractThis paper presents the quality evaluation of the data products from India's first SAR viz. Radar Imaging Satellite (RISAT-1) in High Resolution Spotlight (HRS) Mode having circular polarimetry from space. Sample scenes of Level-2 terrain corrected georeferenced products are acquired in different regions to observe geometric data quality in terms of Location accuracy and Internal Distortion. Further, parameters are identified to evaluate the image and radiometric data quality, such as Background to Peak Ratio (BPRatio), Integrated Side Lobe ratio (ISLR), Peak to Side Lobe ratio (PSLR), Radar Cross Section (RCS) of the Corner Reflector (CR), geometric resolution in the circular polarization mode (Level-1 Single Look Complex products). Results of the analysis are encouraging and meets the specifications. Location accuracy is better than 80m across track and 110m along-track, which is better than the SAR processor specifications. Further, geometric resolution achieved is within the range of 1.18 m for azimuth direction and 0.75 meter for range direction. RCS from image matched well with the CR's. Maneesha Gupta, Vaibhav Malhotra, Bankim Shah, Shilpa Prakash, Anuja Sharma, B. Kartikeyan |
IGARSS | 1 |
| 2019 | A closed-loop ASIC design approach based on logical effort theory and artificial neural networks
Kunwar Singh, Satish Chandra Tiwari, Maneesha Gupta |
Integr. | 3 |
| 2018 | High bandwidth transimpedance amplifier using FGMOS for low voltage operation
Urvashi Bansal, Maneesha Gupta |
Integr. | 2 |
| 2018 | Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms
Kunwar Singh, Aman Jain, Aviral Mittal, Vinay Yadav, Atul Anshuman Singh, Anmoll Kumar Jain, Maneesha Gupta |
Integr. | 7 |
| 2014 | Wideband digital integrators and differentiators designed using particle swarm optimisationabstractDigital integrators (DIs) and digital differentiators (DDs) of second, third and fourth‐order based on particle swarm optimisation (PSO) algorithm are presented. A modified particle swarm optimisation (MPSO) algorithm with reducing maximum velocity has been used to optimise the mean square error of the digital operators. Statistical and simulation results have been presented for comparing quality of optimal operators obtained by MPSO, genetic algorithm (GA), two variants of PSO and PSO‐GA hybrid techniques. The results obtained for best solutions by the proposed algorithm are either superior or at par with the basic PSO variants and hybrid techniques. The proposed digital operators have also been simulated using MATLAB, and the results have been compared with that of existing DIs and DDs derived by different optimisation algorithms, to demonstrate the effectiveness of the use of proposed MPSO. The relative magnitude errors (dB) obtained for digital integrators and differentiators are as low as −40 and −35 dB, respectively, which are valid for almost the full band of normalised frequency. Maneesha Gupta, Bhavesh Relan, Richa Yadav, Varun Aggarwal |
IET Signal Process. | 1 |