With no further shrinking of device size, 3-D chip stacking by through-silicon-via (TSV) has been identified as an effective way to achieve better performance in speed and power. However, such solution inevitably encounters challenges in thermal dissipation since stacked dies generate a significant amount of heat per unit volume. We leverage an integrated design methodology of stacked-signal-TSVs to minimize temperature. Based on this structure, a three-stage TSV locating algorithm in global routing is designed. We demonstrate that our results, compared with baseline circuits, have 17% temperature reduction with 3% wiring overhead and no performance loss calculated by 3-D Elmore delay model. Compared with the paper by Cong and Zhang where additional thermal TSVs are inserted, our experimental results have in average 23% less TSVs with the same temperature constraint. Compared with the paper by Pathak and Lim, where movable signal TSVs are relocated to reduce temperature in hotspot regions, our result has 8% more temperature reduction with the same number of signal TSVs.

With no further shrink of device size, three dimensional (3D) chip stacking by Through-Silicon-VIA (TSV) has been identified as an effective way to achieve better performance in speed and power. However, such solution inevitably encounters challenges in thermal dissipation since stacked dies generate significant amount of heat per unit volume. We leverage an integrated architecture of stacked-signal-TSVs to minimize temperature with small wiring overhead. Based on the structure of stacked signal TSV, a two-stage TSV locating algorithm in global routing is designed. By this TSV locating algorithm, we demonstrate that our stacking signal TSV structure is able to reduce 17% temperature with 4% wiring overhead and 3% performance loss calculated by 3D Elmore delay model. Compared to a previous work by Cong and Zhang [1] where additional thermal TSVs are inserted, our experimental results have in average 23% less TSVs than Cong and Zhang's [1] with the same temperature constraint.

Providing high vertical interconnection density between device tiers, through silicon via (TSV) offers a promising solution in 3D IC to reduce the length of global interconnection. However, some design issues hinder TSV from volumes of adoption, such as IR drop, thermal dissipation, current delivery per package pin and various voltage domains among tiers. To tackle these problems, the design of power network plays an important role in 3D IC. A new integrated architecture of stacked-TSV and power distributed network (STDN) is proposed in this paper. Our new STDN serves triple roles: power network to deliver larger current and reduce IR drop, thermal network to reduce temperature, and decoupling capacitor network to reduce power noise. As well, it helps to alleviate the limitation of the number of IO power pins. For both single and multiple power domains, the proposed STDN architecture demonstrates good performance in 3D floorplan, IR drop, power noise, temperature, area and even the total length of signal connections for selected MCNC benchmarks.

Unused spare cells occur inevitably in traditional engineering change order (ECO) design flow. It results in inefficient area usage, more leakage, and more IR drop impacts. To tackle these problems, a reconfigurable cell is proposed, which serves the dual purposes of decoupling capacitance and spare cell in this paper. Before ECO is applied, these cells are preplaced as decoupling capacitors. When ECO is applied, these cells are configured as functional cells. To demonstrate the efficiency of our configurable cell, we propose an algorithm for timing closure and IR drop minimization. Compared with traditional ECO flow, our method shows 15% reduction in maximum IR drop and 9% reduction in leakage before applying ECO, and 7% reduction in maximum IR drop after applying ECO, with 10% area of spare cells. In addition, we show that there remain less unsolved timing-violation paths after applying our ECO timing optimization flow due to less IR drop and free selection of ECO gate type.

Unused spare cells occur inevitably in traditional ECO design flow. It results in inefficient area usage, more leakage, and more IR drop impacts. To tackle these problems, a reconfigurable cell is proposed which serves the dual purposes of decoupling capacitance and spare cell in this paper. Before Engineering Change Order (ECO) is applied, these cells are pre-placed as decoupling capacitors. When ECO is applied, these cells are configured as functional cells. To demonstrate the efficiency of our configurable cell, we propose an algorithm for timing closure and IR drop minimization. Compared with traditional ECO flow, our method shows 16% reduction in maximum IR drop and 56% reduction in leakage before applying ECO, and 8% reduction in maximum IR drop after applying ECO, with 10% area of spare cells. In addition, we show that there are less unsolved ECO timing paths left after applying our ECO timing optimization algorithm due to free selection of ECO gate type.