High-rate short-length error correction codes are crucial for ultralow-latency communication (ULLC) applications prevalent in next-generation communication systems. Recent promising developments in this regard include the code-agnostic family of guessing random additive noise decoding (GRAND) decoders. However, they are not directly applicable to multiuser communication scenarios (e.g., in 5G and 6G) characterized by nonorthogonal multiple access (NOMA). To address this gap, we propose a novel multiuser ordered symbol switch (MOSS)-GRAND decoder operating on symbols (instead of bits) to jointly decode the information of a pair of users accessing the channel using NOMA. We also propose a NOMA-successive interference cancellation (SIC) decoder as a conventional straightforward adaptation of GRAND-based decoders to the NOMA setup. Comparing MOSS-GRAND with NOMA-SIC, we show that the former is amenable to higher throughput due to parallelization and is therefore preferred over the latter for the target ULLC applications. The algorithm is translated into a low-latency hardware architecture, where the distance between the received message and all candidate codewords is calculated in parallel to optimize performance. The experimental results demonstrate that the MOSS-GRAND decoder provides improvements between$5.70\times $and$117.51\times $in throughput, with area reductions between$1.88\times $and$789.79\times $compared to traditional GRAND-based decoders adapted for NOMA. This makes MOSS-GRAND an ideal candidate for ULLC applications on resource-constrained platforms, such as the Internet of Things (IoT) nodes.

The adoption of heterogeneous multicore architectures into deadline-constrained embedded systems has various benefits in terms of schedulability and energy-efficiency. Existing energy-efficient algorithms, in this domain, allocate tasks to their energy-favorable core-types while using dynamic voltage and frequency scaling to reduce energy consumption. However, the practicality of such algorithms is limited due to the underlying assumptions made to simplify the analysis. This article paves the way for more practical approaches to minimize the energy consumption on heterogeneous multicores. Specifically, we investigate the nonlinear impacts that core-frequency and cache-partitioning have on task-executions in a heterogeneous multicore environment. In doing so, we propose an algorithm that exploits this relationship to effectively allocate tasks to specific cores and core-types, and determine the number of cache-partitions for each core. Extensive simulations using real-world benchmarks show the proficiency of our approach by achieving an average and maximum energy savings of 14.9 and 20.4 percent, respectively for core-level energy consumption, and 20.2 and 60.4 percent, respectively for system-level energy consumption.

Fog computing (FC) has emerged as a complementary solution to the centralized cloud infrastructure. An FC node is available in closer proximity to users and extends cloud services to the edge of the network in a highly distributed manner. However, with an increase in streaming and delay-sensitive Internet-of-Things (IoT) applications, FC also needs to address the issue of higher latency while forwarding compute-intensive jobs to remote cloud data centers. Hence, there is a need to investigate the use of computational resources at the edge of the network. Volunteer computing (VC) offers a reduction in the cost of maintaining high-performance computing by making use of user-owned underutilized or idle resources, e.g., laptops and desktop computers closer to fog devices. We propose volunteer-supported FC (VSFC), as a computing paradigm, that explores the interplay of these two distributed computing domains to help minimize inherent communication delays of cloud computing, energy consumption, and network usage. To this effect, we have extended the iFogSim toolkit to support VSFC. Extensive simulations show that VSFC outperforms traditional FC-cloud computing by reducing delay by 47.5%, energy by 93%, and network usage by 92% under normal to heavy load conditions.

Convolutional Neural Networks (CNNs) are influencing major breakthroughs in computer vision by achieving unprecedented accuracy on tasks such as image classification, object detection, landmark detection and semantic segmentation. Owing to high computational complexity of most modern CNN architectures, graphical processing units (GPUs) are being utilized to achieve real-time performance albeit at a high energy cost. Consequently, Field Programmable Gate Arrays (FPGAs) based hardware accelerators are also making their way as they demonstrate GPU-like performance with significantly lower energy consumption that is well-suited for embedded vision applications. In this paper, we employ Hardware/Software Co-Design approach to accelerate Tiny YOLOv3 - an efficient CNN architecture for object detection - by designing a hardware accelerator for convolution, the most complex operation involved in the CNNs. Experimental results show significant performance gains, in the range of 3.9× to 21.3×, over previous implementations of efficient object detection algorithms.

Energy consumption in embedded systems is becoming increasingly important especially with the increase in transistor count that needs to fit in smaller chip areas. This calls for a cross-layer effort to improve the energy consumption of an embedded design including design of energy-efficient algorithms. Consequently, we need to find ways for a programmer to quickly estimate the energy consumption of an algorithm at higher abstraction level. This work contributes towards the development of an assembly-level energy estimation framework for embedded processors. Our framework is based on a hybrid approach of instruction level power analysis (ILPA) and functional level power analysis (FLPA) techniques which results in a higher accuracy comparable to ILPA-based approaches while remaining at a higher abstraction level of FLPA for the modeling of processors. The proposed framework, therefore, provides rapid high-level energy estimation results with an accuracy consistent with the state-of-the-art approaches. As test-cases, we have used the proposed framework for two open-source IP-core processors i.e. MIPS R2000 and LEON3.

Image classification is known to be one of the most challenging problems in the domain of computer vision. Significant research is being done on developing systems and algorithms improving accuracy, performance, area, and power consumption for related problems. Convolutional Neural Networks (CNNs) have shown to give outstanding accuracies for problems such as image classification, object detection, and semantic segmentation. While CNNs are pioneering the development of high accuracy systems, their excessive computational complexity presents a barrier for a more permeated deployment. Although Graphical Processing Units (GPUs), due to their massively parallel architecture, have shown to give performance orders of magnitude better than general purpose processors, the former are limited by their high power consumption and generality. Consequently, Field Programmable Gate Arrays (FPGAs) are being explored to implement CNN architectures, as they also provide massively parallel logic resources but with a relatively lower power consumption than GPUs. In this article, we present FFConv, an efficient FPGA-based fast convolutional layer accelerator for CNNs. We design a pipelined, high-throughput convolution engine based on the Winograd minimal filtering (also called Fast Convolution) algorithms for computing the convolutional layers of three popular CNN architectures: VGG16, Alexnet, and Shufflenet. We implement our accelerator on a Virtex-7 FPGA platform where we exploit the computational parallelization to the maximum while exploring optimizations aimed at improving performance. The resultant design loses only 0.43%, 0.47%, and 0.61% Top-1 classification accuracy for VGG16, Alexnet, and Shufflenet-v1, respectively, while significantly improving throughput, resource, and power efficiency compared to previous state-of-the-art designs.

With the increasing demand for higher performance, the adoption of multicores has been a major stepping stone in the evolution of hard real-time systems. Though the computational bandwidth is increased due to parallel processing, the indispensable interactivity between the hierarchical memory sub-system and multiple cores has further aggravated the already complex worst case execution time (WCET) analysis of tasks. Furthermore, caches have the biggest influence on task execution time, and the inclusion of shared caches further increases the unpredictability of the system. Cache partitioning techniques have been proposed as a counter-measure to decouple the shared cache latency from the WCET. However, existing energy-efficient scheduling algorithms are oblivious to the unpredictable nature of shared caches or cache partitioning techniques, thus, diminishing their applicability to real-world systems. Without considering inter-task cache contention, directly using existing algorithms or attempting to allocate and schedule a taskset with cache-partition assignments can result in cache violations. To overcome this dilemma, we propose a novel approach to model inter-task cache contention as a dependency graph to be used by well-established algorithms to minimize energy consumption. Extensive simulations demonstrate the effectiveness of our approach to minimize energy consumption while also avoiding cache violations.

Convolutional Neural Networks (CNNs) have gained widespread popularity in the field of computer vision and image processing. Due to huge computational requirements of CNNs, dedicated hardware-based implementations are being explored to improve their performance. Hardware platforms such as Field Programmable Gate Arrays (FPGAs) are widely being used to design parallel architectures for this purpose. In this paper, we analyze Winograd minimal filtering or fast convolution algorithms to reduce the arithmetic complexity of convolutional layers of CNNs. We explore a complex design space to find the sets of parameters that result in improved throughput and power-efficiency. We also design a pipelined and parallel Winograd convolution engine that improves the throughput and power-efficiency while reducing the computational complexity of the overall system. Our proposed designs show up to 4.75× and 1.44× improvements in throughput and power-efficiency, respectively, in comparison to the state-of-the-art design while using approximately 2.67× more multipliers. Furthermore, we obtain savings of up to 53.6% in logic resources compared with the state-of-the-art implementation.

Energy-efficient scheduling has become an essential branch in the evolution of real-time systems due to requirements for reliability and portability. Such scheduling algorithms exploit the varying voltage/frequency capability of a processor to reduce its energy consumption. However, most of these algorithms assume an inaccurate linear correlation between memory latency and core frequency. To make the matter worse, the inclusion of caches has tarnished the predictability of such systems while also increasing the total energy consumption. Therefore, improved system and task models are crucial for further progression in this domain. In this paper, we propose improvements to existing models in order to incorporate the above-mentioned complexities. We then propose techniques to minimize core-, cache-and system-level energy consumptions. Extensive simulations demonstrate the effectiveness of our approach and the impact each proposed technique has on total energy consumption of the processor.

As real-time embedded systems are evolving in scale and complexity, the demand for a higher performance at a minimum energy consumption has become a necessity. Consequently, many embedded systems are now adopting multicore architectures into their design. However, scheduling on multicores is not a trivial task and scheduling to minimize the energy consumption further increases the complexity of the problem. This problem is especially aggravated for hard real-time systems where failure to meet a deadline can be catastrophic. Such scheduling algorithms yearn for a polynomial time complexity for the task-to-core assignment problem with an objective to minimize the overall energy consumption. There is now a trend toward heterogeneous multicores where cores differ in power, performance, and architectural capabilities. The desired performance and energy consumption is attained by assigning a task to the core that is best suited for it. In this article, we present a survey on energy-efficient multicore scheduling algorithms for hard real-time systems. We summarize various algorithms reported in the literature and classify them based on Partitioned, Semi-Partitioned, and Global scheduling techniques for both homogeneous and heterogeneous multicores. We also present a detailed discussion on various open issues within this domain.

We consider a two-user non-orthogonal-multiple-access (NOMA) communication channel with an iterative multi-user receiver. It is known that NOMA provides performance gains over conventional orthogonal-multiple-access, but it comes at the cost of increased decoder complexity. Moreover, the decoder complexity varies with fraction of duration in which the users' transmissions overlap using NOMA. For this scheme, we present a hardware-friendly implementation of an LDPC-code-based multi-user-detector (MUD). We also present a MATLAB-based high-level design-automation tool that generates hardware descriptions of different NOMA-receivers. Results indicate that the simplified MUD design results in significant area and power savings with negligible impact on performance.

Wireless Sensor Networks (WSNs) are relatively new and challenging research area for embedded design automation. Engineering a WSN node hardware is a difficult job as the design must satisfy several constraints. Among these constraints, overall energy consumption and node size, are the two most significant constraints. WSN node platforms have until recently been designed using off-the-shelf low-power microprocessors (MCUs), even though energy profile of these MCUs is not suitable for ultra low-power sensor nodes. On the other hand, WSN-specific hardware accelerators have also been proposed that have excellent energy profile but lack in flexibility, need higher design efforts and have huge non-recurring engineering (NRE) costs. In this work, we propose an automated system level design flow for an intermediate approach, based on the concept of data path merging (DPM) where several hardware accelerators (called micro-tasks) share a common customized data path, to have an improvement in flexibility and silicon area with possible increase in dynamic power consumption for the control/processing part of the sensor node targeted for field programmable gate array (FPGA)-based implementation. Our experiments show that component-level DPM yields to savings from 20%, to 75% for various FPGA resources like I/O ports, area for combinational and sequential logic, and static power consumption.

Wireless sensor networks (WSN) is a new and very challenging research field for embedded system design automation. Engineering a WSN node hardware platform is known to be a tough challenge, as the design must enforce many severe constraints, among which energy dissipation is by far the most important one. WSN node devices have until now been designed using off-the-shelf low-power microcontroller units (MCUs), even if their power dissipation is still an issue and hinders the widespread use of this new technology. In this work, we propose a complete system-level flow for an alternative approach based on the concept of hardware microtasks, which relies on hardware specialization and power gating to drastically improve the energy efficiency of the computational/control part of the node. Our case study shows that power savings between one to two orders of magnitude are possible w.r.t. MCU-based implementations.

Wireless Sensor Networks (WSN) are a new and very challenging research field for embedded system design automation, as their design must enforce stringent constraints in terms of power and cost. WSN node devices have until now been designed using off-the-shelf low-power microcontroller units (MCUs), even if their power dissipation is still an issue and hinders the wide-spreading of this new technology. In this paper, we propose a new architectural model for WSN nodes (and its complete design-flow from C downto synthesizable VHDL) based on the notion of micro-tasks. Our approach combines hardware specialization and power-gating so as to provide an ultra low-power solution for WSN node design. Our first estimates show that power savings by one to two orders of magnitude are possible w.r.t. MCU-based implementations.

Engineering hardware platform for a Wireless Sensor Network (WSN) node is known to be a tough challenge, as the design must enforce many severe constraints, among which energy dissipation is by far the most challenging one. Today, most of the WSN node platforms are based on low cost and low-power programmable micro controllers, even if it is acknowledged that their energy efficiency remains limited and hinders the wide-spreading of WSN to new applications. In this paper, we propose a complete system level flow for an alternative approach based on the concept of hardware micro-tasks, which relies on hardware specialization and power gating to dramatically improve the energy efficiency of the computational part of the node. Early estimates show power saving by more than one order of magnitude over MCU-based implementations.

In this paper, we propose an approach combining the use of distributed hardware tasks implemented as finite state machines (FSM) and power gating techniques to obtain ultra low-power implementations. We target for control dominated applications represented as control task graphs, and propose a complete flow including a C to hardware task compiler. Our approach is validated experimentally and shows impressive improvement over software implementation on leading edge low-power microcontrollers such as the MSP430.