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Pramod V. Argade

dblp:61/89 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Performance modeling and evaluation · 62% Electronic design automation · 21% Integrated circuit design · 10%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 6 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation › simulation › architectural simulation
full-system simulation		 0.011994
A Technique for Monitoring Run-Time Dynamics of an Operating System and a Microprocessor Executing User Applications · ASPLOS 1994
Performance modeling and evaluation
simulation		 0.011994
A Technique for Monitoring Run-Time Dynamics of an Operating System and a Microprocessor Executing User Applications · ASPLOS 1994
Performance modeling and evaluation
workload characterization		 0.011994
A Technique for Monitoring Run-Time Dynamics of an Operating System and a Microprocessor Executing User Applications · ASPLOS 1994
Electronic design automation › timing analysis
delay modeling		 0.011989
Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Integrated circuit design
digital circuit design		 0.011989
Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation › circuit sizing
transistor sizing		 0.011989
Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989

Methods — techniques the papers use, named apart from their topics

microprocessor simulation · 0.0hardware development system · 0.0newton-raphson numerical method · 0.0iterative device sizing · 0.0ADVICE simulation · 0.0
YearPublicationVenuePosition
1994 A Technique for Monitoring Run-Time Dynamics of an Operating System and a Microprocessor Executing User Applications
abstract
In this paper, we present a non-invasive and efficient technique for simulating applications complete with their operating system interaction. The technique involves booting and initiating an application on a hardware development system, capturing the entire state of the application and the microprocessor at a well defined point in execution and then simulating the application on microprocessor simulators. Extensive statistics generated from the simulators on run-time dynamics of the application, the operating system as well as the microprocessor enabled us to tune the operating system and the microprocessor architecture and implementation. The results also enabled us to optimize system level design choices by anticipating/predicting the performance of the target system. Lastly, the results were used to adjust and refocus the evolution of the architecture of both the operating system and the microprocessor.
Pramod V. Argade, David K. Charles, Craig Taylor
 ASPLOS1
1989 Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS
abstract
A general procedure to size an inverter which drives a given capacitance load and which has precise pull-up and pull-down delays is discussed. This procedure is an iterative combination of a Newton-Raphson numerical method used to size the transistors, and ADVICE simulations to extract parameters used in the delay model for the inverter. The numerical method makes it possible to satisfy the delay constraints precisely, while ADVICE simulations ensure accuracy. This device-sizing procedure is then used to determine the sizes of inverters in two paths, one consisting of two inverters and the other three, each driving an arbitrary capacitive load, such that the complementary output of the two paths has minimal skew and pulsewidth distortion irrespective of the processing variations. A fully automatic procedure to achieve this requires only four ADVICE simulations and takes about four minutes of CPU time on an AMDAHL-5870 computer. The circuit designed by this procedure also has a very small skew and pulsewidth distortion with temperature variation with V/sub DD/ variation, and with the input rise and fall-time variations.>
Pramod V. Argade
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1