The growing number of security threats and vulnerabilities in automotive and industrial control systems motivates the design of Controller Area Network (CAN) bus components with enhanced security measures while maintaining compatibility with existing standards and allowing for interoperability with non-enhanced systems. We present such an enhancement that is implemented by replacing standard CAN bus transceivers with a new transceiver that permits automatic authentication of CAN frames. The theoretical basis of our approach is based on incorporating a secondary communications channel in a virtual manner that simultaneously transmits an authentication signature with each CAN frame. To implement the authentication mechanism, a new backward-compatible transceiver is described, designed and validated that implements the virtual channel through selectively delaying the rising edges in a Non-Return-to-Zero (NRZ) waveform that encodes a CAN frame at the physical layer. Novel aspects of the CAN transceiver include the use of use of authentication signature generators and comparators, rising edge time-based modulator/demodulator circuitry, and phase-preserving rail converters. The mixed-signal transceiver circuit was fabricated using a$0.18\mu $m CMOS process and operation was validated over PVT corner cases and with non-secure transceivers to demonstrate backward compatibility.

A new CAN bus transceiver integrated circuit is described that incorporates an inherent auxiliary data channel. The auxiliary data channel enables CAN packet authentication signatures to accompany primary data payloads. The transceiver is backward compatible with the CAN protocol and thus may be used within existing networks with no modifications required. The clock edge at the transmitter is phase modulated with signature data in a manner that does not exceed clock jitter tolerances in the CAN specifications. The receiver is designed to recover the primary data and the packet signature. By comparing the received signature with the authorized packet signature, a “Go/No Go” output indicates if the received packet is properly authenticated.

We present an RF sampling 1 GS/s 12-bit single-channel successive approximation register (SAR) assisted pipeline analog to digital converter (ADC). A novel Harmonic-injecting Cross-Coupled Pair (HXCP) is proposed in a$\text{G}_{\text {m}}$-R based residue amplifier design as a critical part of the presented ADC. This technique overcomes the challenges in designing analog amplifiers using advanced nanometer CMOS processes and achieves the gain and linearity required for the ADC. By implementing the HXCP in a residue amplifier (RA), the proposed technique successfully improves the RA linearity by at least 10 dB and meanwhile boosts the gain of the RA to be about 8. The entire ADC consists of three stages each with 4-bit, 4-bit, and 6-bit, respectively. Two one-bit interstage redundancies are implemented between the three stages. Various techniques are also implemented to help the ADC achieve the targeted speed and resolution. The presented ADC was implemented in a 28nm CMOS process and achieves an ERBW of 1 GHz, an SNDR of 60.7 dB, an SFDR of 73 dB at Nyquist input (495 MHz) and an SFDR of 82 dB at 1 GHz input. A 7.5 fj/conv-step FoMwand a 169.4 dB FoMs are achieved, which demonstrate one of the best Figure of Merits (FoMs) among ADCs of similar speed and resolution.

This article presents a 2.56-GS/s 12-bit eight-channel interleaved analog-to-digital converter (ADC) that achieves an FOM$_{S}$of 156.6 dB at near the Nyquist input frequency of 1.2 GHz in 65-nm CMOS technology. A new technique is employed to mitigate the effect of comparator metastability. In addition, a noise averaging calibration method is implemented to calibrate the comparator offset in each subchannel in the foreground. Moreover, a digital-to-time delay tuner is employed to minimize the time skew among the eight channels. Several other calibration techniques are also employed to reduce the interchannel and intrachannel nonidealities. The single subchannel ADC achieves an SNDR of 59.6 dB and an FOM$_{S}$of 167.3 dB at the Nyquist input frequency with a sampling rate of 350 MS/s. With eight subchannels interleaved, the 2.56-GS/s ADC achieves an SNDR of 55.7 dB and an SFDR of 64 dB at the Nyquist input with calibration. In addition, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the interleaved ADC are 0.51/−0.4 LSB and +1.38/−0.89 LSB, respectively.

This paper presents a fully-integrated 76-81 GHz four-channel digitally controlled receiver (RX) in 65-nm CMOS, which utilizes a four-channel RX front-end with high linearity, an LO distribution network, and a reconfigurable 4-channel analog baseband (ABB). It achieves high integration level and is capable of flexible reconfigurability automotive radars with wide and flattened temperature characteristic. Each RX front-end consists of a low noise amplifier (LNA) employing a neutralized common source (CS) with configurable high-linearity and an active mixer with linearity-priority design. Additionally, a bias circuit with positive temperature coefficient is used for temperature compensation of the millimeter wave (mm-Wave) amplifiers and mixer. The RX chain offers tunable gain and bandwidth (BW) with digital control and bandwidth tuning for the ABB. The measured results show that the RX achieves an input 1-dB compression point (Pin,1dB) of -7 dBm and a noise figure of 11-26 dB across a temperature range from -45 to +125°C, both over the range of 76-81 GHz. The RX has a tunable gain from 18 to 66 dB over the 3-dB programmable IF BW from 0.1 to 10 MHz. The power consumption of the entire receiver is 0.52 W.

In this article, an asynchronous serial transceiver that is capable of transmitting and receiving an auxiliary data stream concurrently with the primary data stream is described. The transceiver instantiates the auxiliary data stream by modulating the phase of the primary data without affecting the primary channel transmission and recovery mechanisms. Standard receiver interoperability is maintained since the auxiliary data appear as primary data jitter. Analysis of the proposed transceiver and considerations of the system parameters are included and can be used to determine how such an auxiliary channel is implemented. The proposed transceiver with the auxiliary channel can be widely used in many data communication applications such as for transmitting signatures for authentication or other control information, steganography, or additional data in an existing serial link. A prototype transceiver, implemented in a 65-nm CMOS process, demonstrates the proposed concept with an 80-Mb/s auxiliary channel in a 2.56-Gb/s asynchronous serial link.

This paper presents a 77 GHz Receiver (Rx) for automotive radar with high linearity, low noise figure (NF) and reconfigurable gain and bandwidth of the analog baseband (ABB), implemented in TSMC 65 nm CMOS general purpose (GP) technology. The Rx includes a low-noise amplifier (LNA), sharing the transconductance stage with a double-balanced mixer, an LO chain with a frequency doubler and an analog baseband. The entire Rx consumes 123 mW. Measurement results show that the input 1 dB compression point (P1dB) is -14 dBm at 81 GHz, a conversion gain (CG) of 20.5-62.5 dB is digitally tunable at 77 GHz, and an NF of 11.2-18.3 dB is achieved over the frequency range of 76-81 GHz.

The term CyberSecurity means many different things to many people - some think of data security, some think of identity protection, some think of intrusion attacks on the internet or USB ports. In reality, CyberSecurity represents any type of attack on computing machines. One of the type of attacks that is often overlooked are attacks by the supply chain to inject malfeasant circuitry into semiconductor devices as they are made. This is the one aspect of Design-for-Security and Design-for-Trust that is usually ignored. This innovative practice session will highlight three talks on hardware CyberSecurity attacks and defenses from both industry and academia.

This paper presents a 1-GS/s 3.2-mW 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) using background-calibrated coarse and fine comparators. A coarse and fine comparator scheme is proposed for the bit cycling procedure of MSBs and LSBs to reduce the power consumption. By employing a capacitive digital-to-analog converter (DAC) with redundancy, the decision errors of the coarse comparators due to the thermal noise can be tolerated. Therefore, coarse comparators can have relaxed noise constraint and consume low power. In addition, a novel background calibration method is proposed to align the offsets between different comparators using a reference comparator. This background calibration technique requires no additional bit cycle for comparator calibration, thus improving the ADC's conversion speed. The prototype ADC is implemented in a 28-nm CMOS technology and achieves an effective number of bits of 6.95 b (signal to noise and distortion ratio (SNDR) of 43.6 dB) near Nyquist frequency with the figure of merit (FOM) of 25.87 fJ/conversion-step. To the best of authors' knowledge, this ADC achieves the highest SNDR among all single-channel SAR ADCs reported that operate above 1 GS/s.

Variations in test fallout during the testing of high-volume devices may arise from a variety of sources. Some of these, such as process variations and design marginalities, correspond to actual problems with the devices being tested and should lead to those devices being scrapped and/or changes being made to the fabrication process. However, in other cases, the test equipment itself could be unreliable or require an alteration in the test procedure, leading to either bad chips tested as good or good chips failing the test. Thus, a real-time monitor of the yield data and the quality of the test result data is essential for assuring high test quality and for ruling out possible issues arising from the test hardware. The real-time monitoring of the yield can save the chip manufacturer time and cost by finding issues with the testing system in the early stages of production (or as soon as those issues arise), avoiding the scrapping of good devices, and preventing the penalty of sending bad units to the customer. In this paper, a low-cost algorithm to monitor the yield of multiple test sites is presented. The method is capable of being implemented in the test program of a standard tester, and the ability of the approach to provide early warning of test site problems during wafer test is demonstrated through an industrial case study.

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over 4-8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme enabling continuous data rate support. The digital architecture not only eliminates the large filtering capacitor but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm2in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. The measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the synchronous optical networking (SONET) OC-192 jitter tolerance mask at least by 0.2 unit interval at high frequencies (4-100 MHz) with a 231- 1 pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of 10-12.

This paper presents a low-power 10-Gb/s vertical cavity surface emitting laser (VCSEL) driver integrated circuit (IC) with electrostatic discharge (ESD) protection in the 130-nm CMOS technology. A distributed amplifier (DA)-based modulator is proposed to boost the driver bandwidth. It employs artificial transmission lines to cancel the device parasitic capacitances of the driver. A distributed ESD protection technique is applied to equalize the group delay of the DA to optimize the jitter performance. To minimize the silicon area, the optimal number of DA taps in the proposed modulator has been derived. To compensate for the capacitive load and the channel losses at the output of the driver, a frequency-domain preemphasis scheme is proposed. The proposed DA modulator occupies an area of 0.69 mm2, and the entire driver IC has a die size of 2 mm×2 mm, including the pads. Both electrical and optical tests have been carried out to characterize the performance of the proposed VCSEL driver IC. Measurements at a data rate of 10-Gb/s demonstrate a typical power consumption of 85 mW under a single 2.5 V supply voltage (49 mW, if separate 1.2 and 2.5 V supplies are used) and an rms jitter of 0.63 and 1.12 ps for the electrical test and optical test, respectively.

Repeatability, isolation and accuracy are the most desired factors while testing wireless devices. However, they cannot be guaranteed by traditional drive tests. Channel emulators play a major role in filling these gaps in testing. In this paper we present an efficient channel emulator which is better than existing commercial products in terms of cost, remote access, support for complex network topologies and scalability. We present the hardware and software architecture of our channel emulator and describe the experiments we conducted to evaluate its performance against a commercial channel emulator.

In this paper, the design and simulation of a CMOS ultra-wideband (UWB) transmitter using TSMC 0.18 μm CMOS technology is presented. The operating frequency band of the transmitter is from 3 to 10 GHz for the application of UWB communications. The structure of the transmitter is based on the current-steering digital-to-analog converter (DAC). The design has the feature of high-tunability and easy adoption of modulations. The simulation results show that the output of the transmitter complies with the FCC regulations and has a power consumption of 32 mW at a 50 MHz pulse repetition frequency (PRF).

A Δ-Σ fractional-N Phase-locked Loops (PLL)- based frequency synthesizer (FS) with a frequency range of 250 MHz to 4 GHz is presented. By employing the Δ-Σ fractional-N technique and utilizing the multi-phase clocks available in the ring-VCO of the PLL, the frequency synthesizer is capable of generating high-resolution and low-spur clocks with instant frequency switching. Moreover, the proposed FS has the ability to adjust clock duty cycle which is needed in applications such as time-interleaved ADCs, switched-capacitor circuits, and DC-DC converters.

Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, Fractional-N architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is based on a new concept, Time-Average-Frequency, to generate frequencies. This paper presents an in-depth analysis and comparison between the two methods.

A frequency synthesizer architecture with a wide tuning range and reduced fractional spurs is presented. The proposed topology includes a Σ-Δ fractional-N synthesizer and an integer Flying-Adder architecture. Compared to the conventional Σ-Δ fractional-N frequency synthesizer, this approach has much wider tuning range. Compared to the fractional Flying-Adder frequency synthesizer, the proposed approach can achieve the same frequency resolution with reduced fractional spurs and alleviates the constraints on the adder design in the Flying-Adder architecture.

The Flying Adder (FA) architecture is one of the latest developments in the area of on-chip frequency synthesis. It has two operating modes: integer-FA mode and fractional FA mode. In the fractional FA mode, a concept of Time-Average-Frequency is used to synthesize certain frequencies that cannot be easily obtained using traditional methods. The issue of using Time-Average-Frequency to drive digital systems has been studied in previous publications by the authors. In this paper, we investigate the impact of using Time-Average-Frequency based clock signals to drive systems with embedded Digital-to-Analog Converters (DAC).

Source-synchronous double-data-rate (DDR) signaling is widely used in electrical interconnects to eliminate clock recovery and to double communication bandwidth. This paper describes the design of a parallel optical transceiver integrated circuit (IC) that uses source-synchronous DDR optical signaling. On the transmit side, two 8-b electrical inputs are multiplexed, encoded, and sent over two high-speed optical links. On the receive side, the procedure is reversed to produce two 8-b electrical outputs. The proposed IC integrates analog vertical-cavity surface-emitting lasers (VCSELs), drivers and optical receivers with digital DDR multiplexing, serialization, and deserialization circuits. It was fabricated in a 0.5-/spl mu/m silicon-on-sapphire (SOS) complementary metal-oxide-semiconductor (CMOS) process. Linear arrays of quad VCSELs and photodetectors were attached to the proposed transceiver IC using flip-chip bonding. A free-space optical link system was constructed to demonstrate correct IC functionality. The test results show successful transceiver operation at a data rate of 500 Mb/s with a 250-MHz DDR clock, achieving a gigabit of aggregate bandwidth. While the proposed DDR scheme is well suited for low-skew fiber-ribbon, free-space, and waveguide optical links, it can also be extended to links with higher skew with the addition of skew-compensation circuitry. To the authors' knowledge, this is the first demonstration of parallel optical transceivers that use source-synchronous DDR signaling.