Smart wireless techniques are at the core of many today's telecommunication and networked embedded systems where performance are enhanced by intertwining radio frequency (RF) and digital aspects. Therefore their design requires to focus on both domains. Traditional approaches for their simulation rely either on different domain-specific tools or on analog-mixed-signal modeling languages. In the former case, the simulation of the whole platform in the same session is not possible while in the latter case, simulation performance is limited by the computationally most intensive domain (usually RF). We present an extension of the SystemC Network Simulation Library that allows to simulate antenna details and node position together with digital hardware and software. The validation on a real wearable system shows that the proposed simulation approach achieves a good trade-off between accuracy and speed thus allowing fast exploration of various configurations in the early phase of the design flow without recurring to the expensive and time-consuming creation of physical prototypes.

The amazing proliferation of communication technologies for embedded systems opens the way for completely new applications but forces designers to adopt new methodologies to meet time-to-market constraints. Computer-Aided Design (CAD) has been traditionally applied to computers and embedded systems in isolation without considering them as a global inter-connected system. The paper contributes to fill this gap by proposing 1) a communication-aware design flow for network-interconnected embedded systems and 2) a formal framework to efficiently synthesize their network aspects by formulating and solving an optimization problem. Presented case studies show the potentiality of the proposed approach to address heterogeneous scenarios, e.g., related to smart spaces up to the ever-more-mentioned Internet-of-Things.

Simulation of accurate HW models is usually required to verify Embedded SW. However, heterogeneous system simulators do not easily allow it and designers must connect multiple simulators in complex co-simulation environments. This paper proposes the automatic generation of cycle-accurate Simulink blocks from the two most popular HW description languages: VHDL and Verilog. The methodology starts from an IP modeled in one of the two supported HW description languages. Then, it relies on state-of-the-art RTL models abstraction procedure to produce a functionally equivalent cycle-accurate model of the IP. Then, it proposes two alternative mapping and code-generation techniques. The first one relies on the portable FMI standard, while the other one exploits Mathworks' proprietary C MEX S-Functions. These blocks can be easily integrated within Simulink to simulate digital HW components while avoiding to build complex and computationally demanding co-simulation frameworks: a valuable feature when developing complex heterogeneous systems. A set of RTL IPs are used to compare the proposed approach to state-of-the-art co-simulation techniques. Furthermore, the experiments presented in this paper compares the two proposed alternatives to highlight their advantages and drawbacks.

Each year automotive systems are becoming smarter thanks to their enhancement with sensing, actuation and computation features. The recent advancements in the field of autonomous driving have increased even more the complexity of the electronic components used to provide such services. ISO 26262 represents the natural response to the growing concerns in terms of the functional safety of electrical safety-related systems in this area. However, if the functional safety analysis of digital devices is quite a stable methodology, the same analysis for analog components is still in its infancy. This paper aims to explore the problem of fault analysis in analog circuits and how it can be integrated into the design processes with minimum effort. The methodology is based on analog language manipulation, analog fault instrumentation and automatic abstraction. An efficient and comprehensive flow for performing such an activity is proposed and applied to complex case studies.

This paper presents an approach to automatically generate transactors that implement TLM protocols for RTL IPs, such that the RTL IPs can be abstracted towards corresponding TLM models and easily integrated inside a TLM virtual prototype. The obtained transactor is self-adaptive, since it allows plugging the target IP in the virtual prototype independently from the protocol implemented by the corresponding TLM initiator. The transactor is automatically created from the set of PSL assertions that describe the temporal behaviour of the communication protocol of the original RTL IP.

In this paper we present the concepts and the organization of the FP7 Project SMAC (Smart systems Co-design), an Integrated Project (IP) of the 7th ICT Call under the Objective 3.2 "Smart components and Smart Systems integration". We describe in particular the project objectives and its organization, and how it addresses the challenges of the integration of heterogeneous and conflicting domains that emerge in the design of smart systems. The main outcome of the SMAC project is the development of flexible software platform (the SMAC platform) for smart subsystems/components design include methodologies and EDA tools enabling multi-disciplinary and multi-scale modeling and design, simulation of multi-domain systems, subsystems and components at all levels of abstraction, system integration and exploration for optimization of functional and non-functional metrics.

Designers are more and more forced to define innovative models and methodologies for managing integration of heterogeneous components and heterogeneous Chip Multiprocessors (CMPs) in modern embedded systems. In this context, component-based design seems the more promising approach, but it suffers from the lack of a widely adopted Model of Computation (MoC) able to capture component heterogeneity. This paper proposes univerCM, a new model of computation based on the Heterogeneous Intermediate Format (HIF) with the aim of supporting bottom-up design and system integration from a set of heterogeneous components. HW and SW components can be described by means of different languages and according to different MoCs, toward a uniform intermediate description based on a rigorous semantics. A mapping from univerCM to SystemC is proposed then to obtain a homogeneous description intended for fast simulation, that can be also used as starting point for CMP design flows. Experimental results show the effectiveness of univerCM in managing system heterogeneity.

Network design in distributed embedded applications is a novel challenging task which requires 1) the extraction of communication requirements from application specification and 2) the choice of channels and protocols connecting physical nodes. These issues are faced in the paper by adopting UML/MARTE as specification front-end and repository of refined versions of the model obtained by both simulation and analytical exploration of the design space. The emphasis is on using standard UML/MARTE elements for the description of networked embedded systems to allow re-use, tool interoperability and documentation generation. The approach is explained on a case study related to building automation.

Verification and design-space exploration of today's embedded systems require the simulation of heterogeneous aspects of the system, i.e., software, hardware, communications. This work shows the use of SystemC to simulate a model-driven specification of the behavior of a networked embedded system together with a complete network scenario consisting of the radio channel, the IEEE 802.15.4 protocol for wireless personal area networks and concurrent traffic sharing the medium. The paper describes the main issues addressed to generate SystemC modules from Matlab/Stateflow descriptions and to integrate them in a complete network scenario. Simulation results on a healthcare wireless sensor network show the validity of the approach.

The paper presents a design methodology for distributed applications of networked embedded systems. The original contribution is the joint perspective on communication aspects and dependability. The methodology allows to model the dependability requirements of the application under design and the degree of dependability of involved components, like nodes, communication protocols, and channels. By assessing the dependability degree of a candidate solution, the methodology allows to iterate the synthesis process until requirements are met. The effectiveness of the proposed design flow is shown by an actual case study.

Network design in distributed embedded applications is a novel challenging task which requires 1) the extraction of communication requirements from application specification and 2) the choice of a suitable communication infrastructure among physical nodes. These issues are faced in the paper by adopting a middleware-based design flow in which the middleware is also modeled and simulated as a component of the whole system. This way, the communication requirements are extracted from middleware calls and network design consists in the choice among different actual middleware implementations whose communication impact has been characterized. Experimental results on actual boards show the accuracy of the proposed methodology.

Dependability is becoming a key design aspect of today networked embedded systems (NES's) due to their increasing application to safety-critical tasks. Dependability evaluation must be based on modelling and simulation of faulty application behaviors, which must be related to faulty NES behaviors under actual defects. However, NES's behave differently from traditional embedded systems when testing activities are performed on them. In particular, issues arise on the definition of correct behavior, on the best point to observe it, and on the temporal properties of the faults to be injected. The paper describes these issues, discusses some possible solutions and presents a new time-varying network-based fault model to represent failures in a more abstract and efficient way. Finally, the fault model has been used to support the design of a network-based control application where packet losses, end-to-end delay and signal distortion must be carefully controlled.

Next-generation networked embedded systems pose new challenges in the design and simulation domains. System design choices may affect the network behavior and network design choices may impact on the system design. For this reason, it is important -at the early stages of the design flow- to model and simulate not only the system under design, but also the heterogeneous networked environment in which it operates. For this purpose, we have exploited a modeling language traditionally used for System design -SystemC- to build a system/network simulator named SystemC Network Simulation Library (SCNSL). This library allows to model network scenarios in which different kinds of nodes, or nodes described at different abstraction levels, interact together. The use of SystemC as unique tool has the advantage that HW, SW, and network can be jointly designed, validated and refined. As a case study, the proposed tool has been used to simulate a sensor network application and it has been compared with NS-2, a well-known network simulator; SCNSL shows nearly two-order-magnitude speed up with TLM modeling and about the same performance as NS-2 with a mixed TLM/RTL scenario. The simulator is partially available to the community at http://sourceforge.net/projects/scnsl/.