Many applications employ digital-to-analog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise , limits the overall signal-to-noise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatch-shaping DACs exploit built-in redundancy to suppress the DAC noise in the input signal's frequency band. Although mismatch-shaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatch-shaping DAC: the dithered first-order low-pass tree-structured DAC. This design ensures that its DAC noise has a spectral null at dc (i.e., zero frequency) by generating digital, dc-free sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signal-band DAC noise power that can be used to predict worst case performance in practical circuits.

Mismatch-shaping DAC have become widely used in high-performance delta-sigma data converters in recent years. Nevertheless, no theoretical results have been published to date that quantify their performance, so designers have been forced to rely on simulation-based analyses. This paper presents the first theoretical performance analysis of a mismatch-shaping DAC. Specifically, the PSD of the mismatch noise introduced by a first-order tree-structured DAC within a second-order ADC delta-sigma modulator with a midscale constant input signal is derived. This particular mismatch-shaping DAC and delta-sigma modulator configuration was chosen for analysis because it has been demonstrated experimentally to achieve state-of-the-art ADC performance. The choice of a constant midscale input was made because simulation and experimental results suggest that it yields the worst-case performance.