A novel architecture design to speed up the Viterbi algorithm is proposed. By increasing the number of states in the trellis, the serial operation of a traditional add-compare-select unit is transformed into a parallel operation, thus achieving a substantial speed increase. The proposed architecture would increase the speed by 33% at the expense of a fairly modest increase in area, thus becoming an attractive approach in high-speed applications. A simple example is shown to illustrate the proposed algorithm in maximum-likelihood sequence detector. A comparative synthesis is made to compare the proposed architecture with other approaches, and synthesis simulations confirm the projection of the throughput gain. Also, the proposed algorithm is extended to the block-processing architecture, and we show that an additional 50% speedup is achieved.

A novel architecture design to speed up the Viterbi algorithm is proposed. By doubling the number of states in the trellis, the serial operation of a traditional add-compare-select (ACS) unit is transformed into a parallel operation, thus achieving a substantial speed increase. The use of the proposed architecture would increase the speed by 33% at the expense of a fairy modest increase in area, thus removing the Viterbi detector/decoder from the worst case speed bottleneck path in most high-speed applications. A simple example is shown to illustrate the proposed algorithm in a maximum likelihood sequence detector.