EDBT 2026 Demo / reviewers in the wild / expert
Hiroyuki Higuchi
dblp:62/1577
· DBLP profile ↗
7ranked-venue papers
5as first author
0since 2021 · last 2015
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 5 first-authorArtificial intelligence and machine learning · 1Databases, data management, data science and information retrieval · 1Theory of computation · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Databases, data mining, and information retrieval
1 paper |
Data mining · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% | |
| Interdisciplinary, comprehensive, and emerging computing
1 paper |
Computational social science and digital humanities · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Data mining
density estimation |
0.2 | 1 | 2015 | Population Synthesis via k-Nearest Neighbor Crossover Kernel · ICDM 2015 |
Data mining › density estimation
kernel density estimation |
0.2 | 1 | 2015 | Population Synthesis via k-Nearest Neighbor Crossover Kernel · ICDM 2015 |
Computational social science and digital humanities
agent-based simulation |
0.1 | 1 | 2015 | Population Synthesis via k-Nearest Neighbor Crossover Kernel · ICDM 2015 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 2002 | An implication-based method to detect multi-cycle paths in large sequential circuits · DAC 2002 |
Electronic design automation
timing analysis |
0.0 | 1 | 2002 | An implication-based method to detect multi-cycle paths in large sequential circuits · DAC 2002 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1996 | A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines · DAC 1996 |
Electronic design automation › logic synthesis › sequential circuit optimization
sequential machine minimization |
0.0 | 1 | 1996 | A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines · DAC 1996 |
Electronic design automation › logic synthesis › logic optimization
state minimization |
0.0 | 1 | 1996 | A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines · DAC 1996 |
Methods — techniques the papers use, named apart from their topics
k-nearest neighbor · 0.4crossover kernel · 0.4bagging · 0.4static hazard analysis · 0.0implication techniques · 0.0ATPG · 0.0iterative improvement · 0.0binary decision diagram · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | Population Synthesis via k-Nearest Neighbor Crossover KernelabstractThe recent development of multi-agent simulations brings about a need for population synthesis. It is a task of reconstructing the entire population from a sampling survey of limited size (1% or so), supplying the initial conditions from which simulations begin. This paper presents a new kernel density estimator for this task. Our method is an analogue of the classical Breiman-Meisel-Purcell estimator, but employs novel techniques that harness the huge degree of freedom which is required to model high-dimensional nonlinearly correlated datasets: the crossover kernel, the k-nearest neighbor restriction of the kernel construction set and the bagging of kernels. The performance as a statistical estimator is examined through real and synthetic datasets. We provide an "optimization-free" parameter selection rule for our method, a theory of how our method works and a computational cost analysis. To demonstrate the usefulness as a population synthesizer, our method is applied to a household synthesis task for an urban micro-simulator. Naoki Hamada, Katsumi Homma, Hiroyuki Higuchi, Hideyuki Kikuchi |
ICDM | 3 |
| 2013 | An Effective Implementation of a Special Quantifier Elimination for a Sign Definite Condition by Logical Formula Simplification
Hidenao Iwane, Hiroyuki Higuchi, Hirokazu Anai |
CASC | 2 |
| 2004 | Enhancing the performance of multi-cycle path analysis in an industrial setting
Hiroyuki Higuchi, Yusuke Matsunaga |
ASP-DAC | 1 |
| 2002 | An implication-based method to detect multi-cycle paths in large sequential circuitsabstractThis paper proposes a fast multi-cycle path analysis method for large sequential circuits. It determines whether or not all the paths between every flip-flop pair are multi-cycle paths. The proposed method is based on ATPG techniques, especially on implication techniques, to utilize circuit structure and multi-cycle path condition directly. The method also checks whether or not the multi-cycle path may be invalidated by static hazards in combinational logic parts. Experimental results show that our method is much faster than conventional ones. Hiroyuki Higuchi |
DAC | 1 |
| 1999 | Lazy group sifting for efficient symbolic state traversal of FSMsabstractProposes lazy group sifting for dynamic variable reordering during state traversal of finite state machines (FSMs). The proposed method relaxes the idea of pairwise grouping of the present state variables and their corresponding next state variables. This is done to produce better variable orderings during image computation without causing BDD (binary decision diagram) size blowup in the substitution of next state variables with present state variables at the end of image computation. Experimental results show that our approach is more robust in state traversal than the approaches that either unconditionally group variable pairs or never group them. Hiroyuki Higuchi, Fabio Somenzi |
ICCAD | 1 |
| 1996 | A Fast State Reduction Algorithm for Incompletely Specified Finite State MachinesabstractThis paper proposes a state reduction algorithm for incompletely specified FSMs. The algorithm is based on iterative improvements. When the number of compatibles is likely to be too large to handle explicitly, they are represented by a BDD. Experimental results are given to demonstrate that the algorithm described here is faster and obtains better solutions than conventional methods. Hiroyuki Higuchi, Yusuke Matsunaga |
DAC | 1 |
| 1995 | Implicit prime compatible generation for minimizing incompletely specified finite state machinesabstractNo abstract available. Hiroyuki Higuchi, Yusuke Matsunaga |
ASP-DAC | 1 |