Demo Data from EDBT 2026 / reviewers in the wild / expert
Yerang Hur
dblp:62/2048
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 2010
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 2 · 1 first-authorSystems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Embedded and real-time systems · 95% Processor architecture and microarchitecture · 3% Memory systems · 1% | |
| Software engineering, system software, and programming languages
1 paper |
Program verification · 100% |
Topics — the 10 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Embedded and real-time systems › cyber-physical system platforms
hybrid systems |
0.2 | 2 | 2010 | Generating Reliable Code from Hybrid-Systems Models · IEEE Trans. Computers 2010 Hierarchical modeling and analysis of embedded systems · Proc. IEEE 2003 |
Embedded and real-time systems › model-based design
code generation |
0.1 | 1 | 2010 | Generating Reliable Code from Hybrid-Systems Models · IEEE Trans. Computers 2010 |
Embedded and real-time systems › critical systems
safety-critical embedded system |
0.1 | 1 | 2010 | Generating Reliable Code from Hybrid-Systems Models · IEEE Trans. Computers 2010 |
Embedded and real-time systems › embedded software
embedded control software |
0.0 | 1 | 2003 | Hierarchical modeling and analysis of embedded systems · Proc. IEEE 2003 |
Processor architecture and microarchitecture
pipelining |
0.0 | 1 | 1995 | Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study · RTSS 1995 |
Embedded and real-time systems
worst-case execution time analysis |
0.0 | 1 | 1995 | Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study · RTSS 1995 |
Embedded and real-time systems › cyber-physical systems
automated highway systems |
0.0 | 1 | 2003 | Hierarchical modeling and analysis of embedded systems · Proc. IEEE 2003 |
Embedded and real-time systems
cyber-physical systems |
0.0 | 1 | 2003 | Hierarchical modeling and analysis of embedded systems · Proc. IEEE 2003 |
Memory systems
cache |
0.0 | 1 | 1995 | Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study · RTSS 1995 |
Electronic design automation › timing analysis
cache timing analysis |
0.0 | 1 | 1995 | Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study · RTSS 1995 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.2hybrid automata · 0.2hierarchical modeling · 0.0formal semantics · 0.0compositional refinement · 0.0timing schema · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | Generating Reliable Code from Hybrid-Systems ModelsabstractHybrid systems have emerged as an appropriate formalism to model embedded systems as they capture the theme of continuous dynamics with discrete control. Under this paradigm, distributed embedded systems can be modeled as a network of communicating hybrid automata. Several techniques for code generation from these models have also been proposed and commercially implemented. Providing formal guarantees of the generated code with respect to the model, however, has turned out to be a hard problem. While the model is set in continuous time with concurrent execution and instantaneous switching, the code running on an inherently discrete platform, can be affected by the sampling interval, round-off errors, and communication delays between the sensor, controller, and actuators. Consequently, semantic differences between the model and its code can arise with potentially different system behavior. This paper proposes a criterion for faithful implementation of the hybrid-systems model with a focus on its switching semantics. We discuss different techniques to ensure a faithful implementation of the model, and test the feasibility of our concepts by implementing a model heater system. In this heater case study, we successfully eliminate all fault transitions and, thereby, generate code with correct behavior complying with the specification. Madhukar Anand, Sebastian Fischmeister, Yerang Hur, Jesung Kim, Insup Lee 0001 |
IEEE Trans. Computers | 3 |
| 2003 | Modeling Distributed Autonomous Robots Using CHARON: Formation Control Case StudyabstractWe present the modeling and analysis of distributed autonomous robots using the specification language for hybrid systems, called CHARON. Coordination between distributed autonomous robots has attracted researchers of embedded and hybrid systems, since there has been increasing demand for multiple robots working together in a dynamically changing or unknown environment to carry out missions such as search and rescue, cooperative localization, and scouting and reconnaissance. To maximize the capability of performing tasks collaboratively as a team, formation control is one of crucial parts in developing distributed autonomous robots. In this paper formation control of a team of robots is modeled using CHARON and the model is analyzed using simulation with assertion checking capability of the CHARON toolset. Yerang Hur, Rafael Fierro, Insup Lee 0001 |
ISORC | 1 |
| 2003 | Hierarchical modeling and analysis of embedded systemsabstractThis paper describes the modeling language CHARON for modular design of interacting hybrid systems. The language allows specification of architectural as well as behavioral hierarchy and discrete as well as continuous activities. The modular structure of the language is not merely syntactic, but is exploited by analysis tools and is supported by a formal semantics with an accompanying compositional theory of refinement. We illustrate the benefits of CHARON in the design of embedded control software using examples from automated highways concerning vehicle coordination. Rajeev Alur, Thao Dang 0001, Joel M. Esposito, Yerang Hur, Franjo Ivancic, Vijay Kumar 0001, Insup Lee 0001, Pradyumna Mishra, George J. Pappas, Oleg Sokolsky |
Proc. IEEE | 4 |
| 1995 | Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case StudyabstractThis paper presents a case study of worst case timing analysis for a RISC processor. The target machine consists of the R3000 CPU and R3010 FPA (Floating Point Accelerator). This target machine is typical of a RISC system with pipelined execution units and cache memories. Our methodology is an extension of the existing timing schema. The extended timing schema provides means to reason about the execution time variation of a program construct by surrounding program constructs due to pipelined execution and cache memories of RISC processors. The main focus of this paper is on explaining the necessary steps for performing timing analysis of a given target machine within the extended timing schema framework. This paper also gives results from experiments using a timing tool for the target machine that is built based on the extended timing schema approach. Yerang Hur, Young Hyun Bae, Sung-Soo Lim, Sung-Kwan Kim, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Chong-Sang Kim |
RTSS | 1 |