Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits is presented. The combination of event driven and bitparallel simulation allows for high accuracy due to the real delay model of the former while maintaining the speedup of the latter. This is demonstrated by detailed experimental results.

A method is presented for the synthesis of optimal regular digital control structures in VLSI circuits. The controllers are modeled as finite-state machines and implemented using counter-based programmable-logic-array structures. Although those structures have already been used in the past, their complete automated design was impossible, due to missing state-assignment algorithms. The state-assignment algorithms presented to close this gap optimize the required silicon area of the controllers. They are divided into two steps: state-chain calculation and state-chain coding. In state-chain calculation the internal states of a finite-state machine are ordered to maximally exploit the counter characteristics. In state-chain coding the internal states are coded so that the state sequences are maintained, while coding constraints are satisfied that permit a further minimization of the circuit.>

The authors present a novel state assignment technique for synchronous finite state machines (FSMs) that are implemented as single programmable logic arrays (PLAs) using Johnson counters as state memories. The goal is to minimize the number of product terms in the PLAs and thus the overall area of the FSMs. The authors use a three-step approach to achieve this. First, the FSM description is adapted to allow an optimal use of the computer properties; then the counter is embedded by ordering the internal states of the FSM; and finally the states are coded. The product term reductions obtained are, on the average 20% to 30% compared to conventional D-latch-based FSM implementations.>

CARLOS, a program system for the automated synthesis of random combinational CMOS logic, is described. The input of CARLOS is a specification of a multiple-output Boolean function in the form of a truth table. CARLOS produces an optimized random logic circuit composed of NAND, NOR, and complex gates under the given fan-in and fan-out limitations. The algorithms implemented in CARLOS are based on logic minimization, novel multiple-output multilevel factoring strategies, and recursive technology mapping. The factorization algorithm performs multiple-output synthesis using an algebraic representation of multiple-output Boolean functions. Tests on a large set of examples have shown the efficiency of the synthesis in terms of circuit size as well as computation time. CARLOS is an integral part of a larger CAD system that supports the automatic logic and physical design of finite-state machines under gate-array constraints.>