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Thomas K. Helstern

dblp:62/2361 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Internet architecture and protocols · 61% Routing and switching · 30% Network management and operations · 9%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 50% Integrated circuit design · 50%

Topics — the 4 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › packaging
multichip module
0.011991
Physical Design Issues for Very Large ATM Switching Systems · IEEE J. Sel. Areas Commun. 1991
Internet architecture and protocols › ISDN
broadband ISDN
0.011990
Functional Architecture for a Next Generation Switching System · INFOCOM 1990
Routing and switching › switching systems
switching architectures
0.011990
Functional Architecture for a Next Generation Switching System · INFOCOM 1990
Network management and operations
operations systems
0.011990
Functional Architecture for a Next Generation Switching System · INFOCOM 1990

Methods — techniques the papers use, named apart from their topics

physical design analysis · 0.0functional reference architecture · 0.0
YearPublicationVenuePosition
1991 Physical Design Issues for Very Large ATM Switching Systems
abstract
The authors examine the physical design issues associated with terabit/second switching systems, particularly with regard to the customer access portion of the switch. They determine the physical design requirements in the areas of backplane interconnections, integrated circuit packaging, and circuit board technology and identify areas where existing- or near-future physical design technologies are inadequate to meet the requirements of this application. A new 3D interconnection architecture that solves some of the problems encountered at the backplane level is suggested. It is also suggested that multichip module technology will help meet some of the speed and density requirements at the chip packaging level. Some of the system-level consequences of the proposed model are discussed.>
Thomas C. Banwell, Renée C. Estes, Sarry F. Habiby, Gary A. Hayward, Thomas K. Helstern, Gail Lalk, Derek D. Mahoney, Donald K. Wilson, Kenneth C. Young Jr.
IEEE J. Sel. Areas Commun.5
1990 Functional Architecture for a Next Generation Switching System
abstract
A functional reference architecture that is intended to meet future switching needs for BISDN (broadband integrated services digital networks) is presented. This includes the ability to support a large variety of potentially complex multimedia services, provide integrated control and operations over all switching resources, accelerate feature introduction, and improve switching system reliability and quality. Open interfaces, particularly for service modules and network-based service logic and operations systems, can support the rapid deployment of new services in a switch-dependent manner. How elements in a next-generation switching system may operate together for a simple call setup in BISDN is presented.>
Thomas K. Helstern, Mario Izzo
INFOCOM1