This paper presents a methodology for full chip RTL timing closure for very large ASIC's. The methodology is based on the concept of a "Silicon Virtual Prototype". The methodology is based on the scalable technique of clustering and cluster placement and leverages the tight integration between the algorithms by means of a common, unified data model.

Article Free Access Share on Issues and answers in CAD tool interoperability Authors: Mike Murray Acuson, Mountain View, Ca. Acuson, Mountain View, Ca.View Profile , Uwe B. Meding Concurrent CAE Solutions, Santa Clara, Ca. Concurrent CAE Solutions, Santa Clara, Ca.View Profile , Bill Berg Mentor Graphics, Wilsonville, Or. Mentor Graphics, Wilsonville, Or.View Profile , Yatin Trivedi Seva Technologies, Fremont, Ca. Seva Technologies, Fremont, Ca.View Profile , Bill McCaffrey High Level Design Systems, Santa Clara, Ca. High Level Design Systems, Santa Clara, Ca.View Profile , Ted Vucurevich Cadence Design Systems, San Jose, Ca. Cadence Design Systems, San Jose, Ca.View Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996Pages 509–514https://doi.org/10.1145/240518.240615Published:01 June 1996Publication History 1citation373DownloadsMetricsTotal Citations1Total Downloads373Last 12 Months40Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Publisher SiteeReaderPDF

This panel discusses the complexities of system designs using textual Hardware Description Languages (HDLs) such as Verilog and VHDL. As the proliferation of circuits and systems design using HDLs continues questions arise as to whether HDL-based programming provides any real productivity gains in the design of complex integrated hardware. Are there are any alternatives, such as graphical or visual formalisms that are perhaps better suited for the task? We start the discussion by examining the relevant features of today's complex hardware systems and the requirements these impose on the modeling language and methodologies.

It is noted that testing ASICs (application-specific integrated circuits) has become a significant problem for engineers; manual generation of test patterns is too time consuming, and automatic generation of test patterns is very difficult, if not impossible, without imposing significant overheads on the design. It is shown that this challenge can be addressed by an innovative solution called CrossCheck. The CrossCheck method fundamentally solves the problem by using a combination of software and hardware techniques. The hardware portion of the technology involves modifying the base array of an ASIC such that it contains a structure similar to a bed of nails. This embedded probe structure provides massive observability within the design, which in turn makes it inherently testable. The software can then take advantage of this testability by providing a set of high-performance tools (typically 40 times faster) which will fault simulate/test generate a broad range of manufacturing defects, including transistor opens and shorts or net opens and shorts. The authors give an overview of the technology and then describe probable defects which may occur in CMOS. They conclude that adoption of CrossCheck allows unprecedented levels of fault coverage and chip or board diagnosis to be achieved.>