A design of low-noise charge sensitive amplifier (CSA) for measurement of optical response of photo-detector registering light produced by semiconductor scintillator is presented. Detailed analysis of the CSA suitable for large parasitic detector capacitance is provided, regarding noise, power and stability. Two scenarios where input transistor is biased in strong inversion and weak inversion are compared, with included accurate 1/f noise modeling. The experimental prototype was implemented in 0.5 μm CMOS process with a 5 V power supply.

A computer configuration design problem where the objective is to configure a parallel processor to do processing in a cost effective manner is examined. The application envisioned is a specialized on-line service that rents time on its machine. The combinatorial optimization problem involved is examined analytically and a heuristic algorithm for its solution is provided. Lessons learned in this work appear in the conclusion.

A novel technique for the numerical extraction of equivalent circuits from physics-based device simulation is presented. The method is based on the partitioning of the device into functional regions, each corresponding to a circuit block. All the circuit elements have a clear physical interpretation. Element values are directly obtained from small-signal dc device simulation. The method generates equivalent circuits of a complexity similar to the traditional approach, with model generation times comparable with those of black-box and physics-based device models. Applications to one-dimensional pn junctions and bipolar transistors are presented, discussing the extraction algorithm in detail.

A bus oriented network where there is a charge for the amount of divisible load processed on each processor is investigated. A cost optimal processor sequencing result is found which involves assigning load to processors in nondecreasing order of the cost per load characteristic of each processor. More generally, one can trade cost against solution time. Algorithms are presented to minimize computing cost with an upper bound on solution time and to minimize solution time with an upper bound on cost. As an example of the use of this type of analysis, the effect of replacing one fast but expensive processor with a number of cheap but slow processors is also discussed. The type of questions investigated here are important for future computer utilities that perform distributed computation for some charge.