Class-D audio amplifiers with a digital feedback path are advantageous when from a digital audio input. The input DAC, which needs to support the full audio resolution, is avoided. A digital loop filter’s transfer function can be realized accurately. Therefore stability can be maintained while maximizing the loop gain within the signal band. On the other hand, a high-resolution ADC is required in the feedback path. The constraints and requirements on the digital loop filter and the ADC are presented. The resulting digital filter can be accommodated within a 100 MIPS digital signal processor. The amplifier is designed to deliver an output power of 4 W to an 8 Ω speaker load. The switching frequency of the power stage is 384 kHz. The digital pulse width modulator operates with a clock frequency of 24.576 MHz. The feedback path uses a continuous time delta-sigma analog-to-digital converter with a sampling frequency of 6.144 MHz and an oversampling ratio of 128. The simulated peak SNDR is 93 dB in a 20 kHz bandwidth. Measurement results are presented from a hybrid prototype with an FPGA-based digital loop filter, discrete-component H-bridge driver and antialias filter, and a continuous-time delta-sigma ADC IC.

Resonance in inductively coupled links improves the gain but reduces the bandwidth and data rate. One of the techniques for increasing the data rate that can be transmitted through a resonant link is to reset the state variables on both the primary and secondary sides of the inductively coupled link after each symbol. This removes inter-symbol interference but reduces the received signal amplitude. Another technique, specific to frequency-shift keying (FSK), is to modulate the resonance frequency of the primary side in accordance with the transmitted frequency. This preserves the signal amplitude but can be applied only on the primary side. This paper compares the performance of these techniques. It is shown that the received signal amplitude is twice as much in resonance-frequency modulation compared to state-variable reset. A new technique combining both these approaches is proposed, and it outperforms all other techniques at high quality factors.

A technique to reduce the area of a low-noise sub-sampling PLL (SSPLL) is proposed. The resistor in the loop filter is eliminated. The transconductor driven by the phase detector is switched such that its output consists of a positive and negative pulse with the former wider than the latter. A low frequency zero can thus be realized with a substantially smaller capacitor. Transconductor noise is suppressed to acceptable levels by the high phase-detector gain. In applications that require low out-of-band phase noise, the capacitance can be reduced by$25\times $or more with typical PLL parameters. A prototype SSPLL from 24.4GHz–29.2GHz with a 50MHz reference clock and bandwidth of 1MHz in 65nm LP CMOS process uses a loop filter capacitance of only 5pF. The conventional topology would require 38pF for the same integrated jitter. The in-band phase noise at 1MHz offset ranges from −90 to −95dBc/Hz, and the out-of-band phase noise at 10MHz offset ranges from −117 to −121 dBc/Hz. The jitter integrated from 10kHz to 50MHz is 330–390 fs. It consumes 18.2mW, exhibiting a minimum FoM of 235dB over the frequency range. The SSPLL occupies an area of only 0.14mm2.

A new method is presented for converting any continuously running discrete-time delta-sigma modulator (DTDSM) into a multi-channel ADC by adding only a digital filter at the output. The inputs are multiplexed and fed to the ADC directly. The crosstalk that would exist if the decimation filter output is demultiplexed directly is canceled using the proposed modulated-sinc-sum digital filter. Compared to resetting the DSM and converting it to an incremental DSM, the proposed technique is at least$1.57\times $more power-efficient. A prototype two-channel ADC clocked at 6.144 MHz with a channel bandwidth of 22 kHz demonstrates the proposed technique. Fabricated in a 180 nm CMOS process, the prototype chip consumes 1 mW/channel, including the digital filters, and achieves a peak SNR/DR of 94.4 dB/98.5 dB. The inter-channel crosstalk is restricted to less than −93 dBc across the entire bandwidth and across temperature.

In principle, the resolution of a successive approximation (SAR) analog-to-digital converter (ADC) can be increased by 1 bit by quadrupling the area and the power dissipation. In practice, due to the increased size of the capacitor array and consequent higher mismatch, the resolution is limited to 12-13 bits. Calibration or trimming can be used to improve the resolution beyond this, but are expensive in area and test time. This work presents a 12-bit SAR ADC embedded in a first-order noise shaping loop to obtain a 16-bit resolution while maintaining sample-by-sample correspondence. Using a sub-quantization DAC in parallel with the LSB DAC allows the conversion cycles to be shorter than the first, increasing the effective sampling rate. Dynamic element matching is used in the 6-bit MSB DAC. The integrator in the loop filter is implemented with minimal overhead using one of the stages of the multistage preamplifier in the comparator. Measurements of a 0.6 μm prototype show 0.7 LSB INL and 0.3 LSB DNL at the 16-bit level and 92 dB peak SNDR for 2.5 kHz input at a 250 kS/s sampling rate.

This work presents a high-linearity, low noise figure, Ku-band (12 to 18 GHz) LNA-Mixer front-end block in a 130 nm SiGe BiCMOS process. A tuned transformer converts the single-ended output of the LNA to a differential signal at its secondary which is coupled directly to the tail nodes of the switching pairs of the Gilbert mixer. The LNA output sees a low impedance, and hence a low output voltage swing. This along with the absence of the extra trans-conductance stage in the mixer enhances its linearity. The measured gain, noise figure, and IIP3 at 16 GHz input are 12 dB, 4 dB, and 4 dBm. This gives a spurious-free dynamic range of 52 dB in a 4 GHz bandwidth. The chip consumes 272 mW and occupies 1mm2.

A new static phase offset reduction technique suitable for low bandwidth delay locked loops is proposed. Chopping, which is a well-known technique for offset reduction, can be easily applied to the phase detector. Applying it to the charge pump is non-trivial and requires complex circuitry. The proposed technique reduces the offset due to both PFD and the charge pump, without actually chopping the latter. Analysis of the proposed method shows an offset reduction at least by a factor of 2. A conventional DLL, a DLL with a chopped PFD, and the proposed DLL were designed in a 130 nm CMOS process to verify the proposed technique. Monte Carlo simulations with random process and mismatch variations show that the offset improves from 19.9 ps in the conventional technique to 1.7 ps in the proposed technique.

A wideband, gain enhanced, high frequency, fully differential operational transconductance amplifier (OTA) with enhanced linearity is proposed. The OTA uses a negative conductance to cancel its output parasitic conductance. An automatic, digitally controlled, feedback tuning loop ensures that the parasitic conductance is tracked across corners. High linearity is achieved by voltage biasing the transistors and allowing higher headroom. The OTA uses a common mode feedback (CMFB) loop for common mode stabilization instead of diode connected transistors which enhances the achievable bandwidth. Simulations in a standard 130 nm CMOS process show a dc gain enhancement from 14 dB to 42 dB when negative conductance in incorporated across process voltage and temperature (PVT). The OTA has an unity gain bandwidth of 20 GHz. It has an input referred noise of 1.75 nV/√(Hz) and has -40dB total harmonic distortion for an input of 330 mVppd.

Mixers in a transmitter typically use pseudo differential common-source baseband amplifiers driving local oscillator (LO) switches. The common-source amplifiers are biased near cut-off for class-AB operation which yields higher efficiency. To mitigate their non-linearity, they are usually preceded by feedback controlled pre-distortion circuitry. DC bias differences between the two pseudo-differential halves of the common-source amplifiers turns out to be a major source of LO leakage. This paper presents an automatic calibration method to reduce the LO leakage. Major contributors of LO leakage in class-AB based power mixers with enhanced linearity and baseband noise filtering is analyzed. Monte Carlo analysis shows that LO leakage is less than -35dBc for 17% of the cases without calibration and 98% of the cases with calibration.

This paper presents a method to determine the scaling factor for different stages in a divider chain(ripple counter) to get the best jitter FoM(minimum jitter times power) with a given divider configuration. An analytic expression for the FoM normalized to the first stage of the divider chain is derived and then optmized to get the best jitter FoM. The analysis shows that scaling down the divider stages in proportion to their input frequency results in a very high jitter and a very poor jitter FoM. For a cascade of divide-by-M stages, each stage should be scaled up by √M compared to the previous stage. Circuit simulation results confirming the analysis are given. When optimally sized, the FoM of a cascade of 8 divide-by-two stages is 14.7 dB better than scaling down the stages successively by a factor of two in order to lower the power dissipation in the low frequency stages. Compared to using 8 identical divide-by-two stages, optimal scaling has a 1.9 dB better FoM.

Tail resonance at double the oscillation frequency is widely used in LC oscillators for reducing phase noise. The phase noise improvement is quite sensitive to shifts in the tail resonance frequency. A 6% error in the tail inductance can cause up to 4 dB increase in the close-in phase noise from the optimum value. Phase noise degradation is quite severe for widely tuned high frequency VCOs where modeling errors and changing output frequency contribute to substantial shift from the desired resonance frequency. We propose a technique to automatically calibrate the tail resonance to obtain the best phase noise. The amplitude of the oscillation across the tail resonant tank is sensed using a peak detector and the capacitor array used to tune this tank is adjusted to maximize this amplitude. This setting maximizes the phase noise improvement due to the tail resonance. A 4 stage left handed LC ring VCO with a tuning range of 8.5 GHz to 13.2 GHz maintains a fairly constant phase noise figure of merit of 190 dBc/Hz for offsets greater than 100 kHz, over the entire tuning range when the proposed technique is incorporated.

An enhanced gain, high frequency, operational transconductance amplifier (OTA) architecture using negative conductance load to cancel its output parasitic conductance across process, voltage, and temperature (PVT) variations without the need of any off-chip intervention is proposed. Simulation results of a prototype transconductor in 0.13μm CMOS process over process corners, 100°C temperature range, and ±10% supply voltage variations show that the DC gain is enhanced from 14dB to 48dB when cancellation using negative conductance is incorporated. A minimum DC gain of 34dB and an average DC gain of 46dB is observed over 500 Monte-Carlo mismatch runs. The OTA has a unity gain bandwidth (UGB) of 20GHz.

Negative feedback is introduced using an integrator as the central element by making intuitive connections with the way we sense the difference between desired and actual values and continuously adjust the latter so that it reaches the desired value. In contrast to the traditional use of a memoryless high gain amplifier as the central element, this approach makes it clear right from the beginning that negative feedback circuits take time to respond (have a finite bandwidth), that some excess delay can be tolerated, while larger excess delays lead to ringing and eventually instability, and that negative feedback circuits can be stabilized by slowing them down. Time domain intuition and analysis lead to key conclusions regarding the stability margin of negative feedback circuits. This approach complements the conventional frequency domain approach by serving as an introduction that anticipates the results that are derived by the latter. The presented approach also lends itself better to synthesis of key negative feedback blocks such as opamps and the phase locked loop.

The opamp and the phase locked loop can be synthesized from the prototype negative feedback system which uses an integrator to continuously drive the output until the error between the desired and actual outputs becomes zero. Different opamp topologies are shown to be logical outcomes of synthesizing such a system and progressively improving its performance. The phase locked loop is synthesized as a frequency multiplier, analogous to a voltage amplifier. The synthetic approach from a common foundation helps students to easily make connections between different negative feedback circuits.

Pulses can be stretched in time by driving them into a filter whose group delay is more than the pulse duration and increasing the time constants of the filter. The stretched pulse can be digitized using a slow analog to digital converter, effectively realizing a high sampling rate for the input signal. This can be used for digitizing short bursts at high speed. The effect of clock jitter is reduced due to the reduced slope of the signal. High order Bessel allpass filters provide a maximally flat group delay and are suitable for this application.

Feedback DAC errors in a ΔΣ analog to digital converter are determined by measuring the idle channel output and removing the DAC elements one by one. This method requires simple computation, does not add excess loop delay, and requires no reconfiguration of the ΔΣ modulator. The errors so determined can be used to correct the output codes in the digital domain or the DAC elements in the analog domain. This technique is a useful alternative to the popular dynamic element matching at high speeds as excess delay cannot be tolerated and at low oversampling ratios where DEM can result in tones. Simulation results indicate that the correction values can be obtained to an accuracy that is sufficient to reduce noise and distortion to nearly ideal levels.

A decimation filter for a low power Delta Sigma (ΔΣ) modulator with 24 kHz bandwidth and an in band resolution of 16 bits is designed with standard cells in a 1.8 V, 0.18μm CMOS process. Retiming, Canonical Signed Digits (CSD) encoding along with optimal selection of data width are coded with a hardware description language (HDL) to obtain optimality for power and an automated design. The filter occupies an area of 0.46 mm2and consumes 100μW from a supply of 1.8 V and is operational down to a supply voltage of 0.9 V. This makes it suitable for use with very low power ΔΣ data converters for digital audio.

Charge pump PLL is prone to reference spurs due to non-idealities like feedthrough, charge pump current mismatch and loop filter leakage. To resolve the problem of reference spurs, a randomization technique that converts the spurs to wideband noise is proposed. The added wideband noise has insignificant contribution to the output phase noise inside the PLL bandwidth. Analytical expressions are derived to study the effect of the randomization on the output phase noise. A 1 GHz output frequency PLL with a bandwidth of 1 MHz and a 20 MHz reference frequency is simulated to test the idea. From the simulated results we could see a spur reduction of 20 dB in the nominal case. The settling time of the simulated PLL measured for a 25.2 ppm settling error is 4.5 μs.