Demo Data from EDBT 2026 / reviewers in the wild / expert
T. G. McDonald
dblp:62/2995
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1975
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 87% Processor architecture and microarchitecture · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital arithmetic circuits |
0.0 | 1 | 1975 | The Two's Complement Quasi-Serial Multiplier · IEEE Trans. Computers 1975 |
Integrated circuit design › digital arithmetic circuits › integer multiplier
two's complement multiplier |
0.0 | 1 | 1975 | The Two's Complement Quasi-Serial Multiplier · IEEE Trans. Computers 1975 |
Processor architecture and microarchitecture › arithmetic unit
arithmetic logic unit |
0.0 | 1 | 1975 | The Two's Complement Quasi-Serial Multiplier · IEEE Trans. Computers 1975 |
Methods — techniques the papers use, named apart from their topics
quasi-serial multiplication · 0.0add-shift multiplication · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1975 | The Two's Complement Quasi-Serial MultiplierabstractThis correspondence develops a multiplier for two's complement numbers, similar to the quasi-serial multiplier which operates on sign magnitude numbers. The method offers an alternative to add shift techniques for low cost two's complement multiplication. T. G. McDonald, Ratan K. Guha |
IEEE Trans. Computers | 1 |