This paper presents the circuit design of a two-stage dynamic comparator optimized for high-speed, high-resolution analog-to-digital converters (ADCs). A conventional double-tail comparator is used as a reference for benchmarking. The proposed comparator is implemented using a 28 nm CMOS process and simulated using the Spectre circuit simulator under a 1 V supply. Theoretical analysis and simulation results prove that the proposed circuit is faster compared to the conventional double-tail comparator, while mantaining the same power consumption. Additionally, the design exhibits reduced noise levels, with an RMS noise voltage of less than 100 μV, making it suitable for low-noise applications. In terms of the Figure-of-Merit (FoM), the proposed comparator achieves 128 μW mV2GHz−1, showing a competitive performance compared to other state-of-the-art designs in the literature. These results highlight the effectiveness of the proposed comparator in applications requiring high-speed, low-power, and low-noise ADCs in advanced CMOS technology nodes.

This paper presents a mixed-signal Silicon Photomultiplier with integrated front-end, including a reconfigurable Pulse Shaper. Each Silicon Photon Avalanche Diode of the msSiPM converts a photon into a programmable current pulse. Then, all analog current signals are collected by a transimpedance amplifier which provides an output voltage proportional to the number of triggered SPADs. By properly tuning the shape of the current pulses, the proposed msSiPM rejects the background light and optimizes the Signal-to-Noise Ratio. As the architecture is mostly digital, msSiPM consumes a low static power consumption, equal to 428$\mu $W. The receiver is composed by a$20 \,\, \times 20$-pixel array, and it is fabricated in a 0.11$\mu $m CMOS technology reaching a pixel fill factor equal to 32.8%. Measurements have been carried out under different background photon fluxes, one stronger and one weaker, corresponding to 4.15 and 2.15 GPhotons/s at the SiPM, demonstrating strong background rejection in both conditions. In addition, a SNR maximization has been verified. Analytical models for SNR and Signal-to-Background Ratio have been presented, showing a good matching with experimental results.

Despite the scaling of the supply voltage of deep-submicrometer CMOS technologies, many applications still require to deal with off-chip signals in high-voltage domains (e.g., 3.3 and 5 V). Hence, foundries offer fabrication processes with voltage-tolerant transistors, which are inherently protected from the electrical stress, at the expenses of compromising their performances, reducing the design portability, and augmenting the production costs in case of the customization of the process. As an alternative, circuit techniques, such as cascoding, adaptive biasing, and voltage shifting, result effective in designing analog circuits, such as amplifiers and voltage drivers at high supply voltage with voltage-scaled transistors. This article presents the architecture of a switch for analog multiplexers (MUXs) able to handle signals up to twice the nominal supply voltage of the employed transistors. To validate the circuit choice, a switch for a 5-V MUX has been designed with 2.5-V transistors in 28-nm CMOS technology. The comparison with a benchmark architecture with tailored 5-V devices shows that an about three times larger area and 4-$\mu \text{A}$static current demand have to be considered. Moreover, an accelerated degradation test (ADT) showed a similar decay of the features of both types of switches.

This paper presents a performance analysis of a system for electrochemical impedance spectroscopy (EIS). The system, composed by an analog front-end (AFE) and a custom microcontroller (MCU) board, performs the impulse response (IR) measurement of linear and time-invariant (LTI) systems with pseudo-random excitation signals. As a novelty, a specific AFE for the interfacing of two-terminal resistive and capacitive sensors is covered in detail. The paper proposes, for the first time, a mathematical model to predict the impact of the main noise sources in the measured IR. Thanks to the proposed approach, the AFE and the system’s parameters can be properly designed in order to reduce the error, thus, minimizing the energy-per-error figure of merit (FOM) as well. The AFE is realized as discrete-components circuit and it has been included in a custom MCU-based measurement system as an expansion module. The predicted results from the mathematical model, in terms of noise power, SNR, and measurement error are validated through system-level simulation and experimental measurements. The system performs the IR measurement with 1023 points, showing root-mean-square (RMS) measurement errors of 1% and 1.4% for the tested ADC sampling frequencies of 62.5 kHz and 125 kHz, respectively. These lead to excellent FOM values of 128.9 mJ$\cdot $%2and 252.6 mJ$\cdot $%2that outstand the state of the art.

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ($40\mu \text{A}$) are required.

An energy-efficient, wide dynamic-range (DR) CMOS analog front-end (AFE) for chemiresistive sensors is presented. The circuit is specifically designed for the Metal Oxide (MOX) gas sensors, a special technology of chemiresistive sensors, broadly diffused in modern portable devices due to their low-cost and simplicity of use. Energy efficiency is mandatory for the AFE in order to prolong the battery life that supply these devices. The proposed circuit implements the resistance-to-time (R-to-T) conversion of the sensor's resistance by adopting a relaxation oscillator-based architecture. A limiting resistor in series with the sensor is introduced for reducing the circuit's energy-per-measurement (EpM), while mitigating the error due to the sensor's parasitic capacitance. The analysis of the circuit is presented with emphasis on the design trade-off between error due to the sensor's parasitic capacitance and power consumption on one side and read-out sensitivity on the other. The chip prototype is realized in AMS 0.35μm process and has been tested in the DR between 100Ω and 4.7MΩ with an accuracy less than 0.1% and a precision less than 0.029%. The efficacy of the presented AFE is proved by adopting the circuit in a real chemical environment with a commercial sensor. The proposed AFE shows a maximum EpM of 296nJ which is three times better than the state of the art.

A 4th-order 28.8MHz low-pass analog filter uses a modified version of Sallen-Key (SK) biquad that solves the standard SK cell critical aspect due to the out-of-band zeros (OoB). The proposed cell completely cancel the OoB zeros by means of a low-power auxiliary path and a specific design optimization.

This paper presents a 4th-order low-pass continuous-time filter with 21.4 MHz bandwidth. Using a positivefeedback in combination with resistors, this architecture synthesizes two complex conjugate poles. The filter is designed and optimized to feature high-linearity along all filter passband, and, in particular, at the cut-off frequency edge. The filter consumes only 100 μA with 1.8V voltage supply, and achieves 45μW/pole power consumption, 300 μVRMSinput-referred noise, 21.9 dBm IIP3 with 2–3 MHz input tones and 12dBm IIP3 near the cut frequency using 19–20 MHz tones.

In this paper a highly linear-dual band RF front-end (LNA and Mixer) for IR-UWB (IEEE 802.15.4a) applications is proposed. LNA exploits a common-gate (CG) stage in parallel to a common-source (CS). It performs single-ended to differential-ended operation, avoiding balun stage. It features 18 dB maximum gain,+11.8 dBm IIP3. The RF front-end receiver has been designed in 65nm CMOS technology consuming 13.5 mW.

The design of an automatic biasing system for High-Electron-Mobility-Transistors is here presented (HEMT-Biasing-System, HBS). The HBS automatically regulates the operating point of an off-chip multistage HEMT block. A proper automatic algorithm is implemented in order to maximize the HEMT transconductance (gm) efficiency (defined as gm/IDSratio). This is an important feature in several HEMT-based systems, since they are used in LNA stages, where noise/power trade-off is a key aspect. Interfacing CMOS and HEMT technologies features several design issues, like negative gate-source voltage (to be managed by a CMOS circuits for HEMT switch-off operation) and closed-loop stability (due to the presence of very large off-chip capacitance - 100nF). The System here presented manages all these issues with tailored circuit solutions. A prototype has been designed in CMOS 0.35μm technology. It consumes 6.2mW (excluding the current consumption for HEMT driving).

In this paper a 5thorder low-pass continuous time analog filter in CMOS 45nm technology is presented. The filter design is based on a single compact cell used to synthesize five poles. The circuit performs the low-pass filtering of the in-band signal, while the in-band thermal noise is high-pass filtered, improving Signal-To-Noise-Ratio. 1-GHz -3dB-bandwidth is obtained by a prototype of the filter simulated in 45nm CMOS technology node (also Process-Voltage-Temperature simulations are available). The overall power consumption is 9mW from a single 1.2V supply voltage. 54dB@THD>40dBc is the SNR at 0dB gain.

In this paper the complete design of a Programmable Gain Amplifier embedded in UWB receiver is presented. The receiver is part of a System-On-Chip placed inside the car tire (with the aim to interchange data with the car control unit) where dynamic stress, temperature and aging are very important issues, resulting in severe design constraints for CMOS analog integrated circuits. Furthermore, the SoC is biased by vibration-based energy scavenger, and a as consequence, very low power is available for the integrated circuits. High input impedance is required from system level constraints and this is achieved with MOS input devices, exploiting dual differential input Opamp. The PGA gain is programmable in the 15dB-to-50dB range with 1dB step. For the maximum gain level (50dB), the Input-Referred-Noise power spectral density is lower than 20nV/vHz. From a single 1V supply, for the minimum gain level (15dB), a 0.8Vzero-peak output signal is processed with THD=−40dBc.

In this paper the design of a 10b 100-MS/s pipeline analog-to-digital converter (ADC) with an optimized bit-stage resolution is presented. A careful analysis of the ADC architecture is presented. The proposed architecture is made by two main stages with opamp-sharing technique and a 3b full-flash ADC. The 1ststage has a 1.5b resolution architecture, the remaining stages have 2.5 b resolution architecture. Furthermore, the input sampling is directly performed on the 1ststage. The ADC is implemented in 65 nm digital CMOS process technology. It achieves 69.3 dB spurious-free-dynamic-range (SFDR), 59.3 dB signal-to-noise ratio (SNR), 9.6 effective number of bits (ENOB) for a 49 MHz input at full sampling rate. The ADC power consumption is about 12.7 mW from a 1.2 V supply. The FOM value is about 165 fJ/conv. It occupies 0.8mm2.

In this paper two different design approaches for a large tuning range LP filter for DVB-T receivers are presented. The LP filter is placed at the beginning of the receiver chain, before to the RF and base band blocks, so that the design is challenging because high out-band frequencies rejection is required while maintaining low input referred noise. Closed-loop topologies have been investigated to comply with the in-band linearity requirements. A system level analysis has been developed using a proper Matlab procedure. This procedure allows optimizing the basic filter parameters - opamp bandwidth, R and C values - in order to satisfy the filter transfer function requirements. Two different design approaches will be considered. The first proposal is based on a 2nd order biquadratic cell. High quality factor is synthesized while guaranteeing the out-of-band frequencies rejection. The second implementation is based on the cascade of two biquadratic cells with more relaxed quality factor requirement. The design is realized using the 90nm CMOS technology. The simulation results for both implementations are presented. The minimum out-of-band rejection is maintained lower than -30dB, the maximum IRN in both cases is 4nV/radicHz and the IM3 is lower than -30dB for two in-band input tones.

We report here the results of some laboratory experiments performed to validate the effectiveness of a technique for the self tuning of integrated continuous-time, high-speed active filters. The tuning algorithm is based on the application of a pseudo-random input sequence of rectangular pulses to the device to be tuned and on the evaluation of a few samples of the input-output cross-correlation function which constitute the filter signature. The key advantages of this technique are the ease of the input test pattern generation and the simplicity of the output circuitry which consists of a digital cross-correlator. The technique allows achieving a tuning error mainly dominated by the value of the elementary capacitors employed in the tuning circuitry. The time required to perform the tuning is kept within a few microseconds. This appears particularly interesting for applications to telecommunication multi-standard terminals. The experiments regarding the application of the proposed tuning algorithm to a baseband multi-standard filter confirm most of the simulation results and show the robustness of the technique against practical operating conditions and noise

In this paper a complete design of an analog 4th order base band filter for WLAN receivers operating at 600mV supply voltage is presented. The design is based on the use of different input and output opamp common mode voltages and on the Input Common Mode Feedback circuit. The ICMFB allows maximizing the overdrive voltages of the opamp input differential pair MOS, guaranteeing the right operating point. The filter is designed using the 0.13μm CMOS technology and features a wide swing performance (DR=68dB@THD=-40dBc when a 800mVpp,differentialsignal is applied at the filter output nodes) and a low power consumption (3.6mW).

A baseband filter synthesizer that takes a behavioural description of the design and produces an efficient transistor level implementation is presented. The tool optimizes the filter at the cascade level, providing the best trade-off between power consumption and dynamic range, and at the cell level, selecting minimum power solutions, through accurate analytical models and an efficient bi-quad topology. Differently from past cascade design techniques based on dynamic range optimization through linear programming, we focus on power minimization while guaranteeing minimum performance levels, given the increasing importance of power savings in hand-held devices. A synthesized filter has been realized in silicon demonstrating the effectiveness of our approach

This paper presents a reconfigurable analog baseband channel for multistandard receivers. The circuit, consisting of two variable gain amplifiers and a low-pass filter, fulfills the requirements of GSM, WCDMA (UMTS), WLAN (IEEE 802.11a/b/g), and Bluetooth. The gain, bandwidth and power consumption of the circuit are changed through a digital control word depending on the selected standard. Simulation results, including all of the tests prescribed by the different standards, confirm the validity of the proposed solution. The in-band IIP3 evaluated with maximum gain (68dB/39dB) is 5dBm/1dBm for UMTS/WLAN respectively, while the power consumption is 51.7mW/55mW in the two cases

The 4th generation of wireless systems needs low-power integrated transceivers that can be reconfigured in order to satisfy different standard requirements. Standard analog blocks are often not suitable for this step towards the future because of their lack of flexibility. We defined a novel approach to make active-Gm-RC biquadratic cells completely reconfigurable. The biquad provides digitally programmable bandwidth and hence power consumption with a fully customizable cut-off frequencies range. Besides, the noise level can be conveniently modified leading to a further power saving. We exemplified the use of this basic building block in the design of a flexible low-pass filter for a zero-IF transceiver. A 2nd/4th/6th order Butterworth filter was implemented with a continuous cut-off frequency tuning between 330 KHz and 24.6 MHz and with a current consumption range between 0.6mA to 26mA

Continuous-time filters are widely used in signal processing but require a tuning system to align their frequency response. Several tuning techniques have been proposed in the literature, which can be grouped in two basic schemes: master-slave and self-calibration arrangements. Here we propose a novel tuning approach which can be applied to both tuning schemes. The tuning algorithm is based on the application of pseudo-random input test pattern signal and on the evaluation of a few samples of the input-output cross-correlation function. The key advantages of the proposed technique are basically the use of a pseudo-random pattern signal which can be generated by a very simple circuit in a small die area and the simple circuitry required to sample the filter output and to perform the cross-correlation operation. Some experimental results of the application of the proposed tuning technique to a benchmark filter are given in order to assess its effectiveness.