Analog computing-in-memory accelerators promise ultra-low-power, on-device AI by reducing data transfer and energy usage. Yet inherent device variations and high energy consumption for analog-digital conversion continue to hinder their wide-scale adoption in mainstream systems. To address these issues, this paper introduces WireLightning, a novel capacitive-computing accelerator featuring a mixed-signal architecture that rethinks analog AI acceleration. Unlike conventional analog crossbars that encode weights in programmable devices, WireLightning exploits intrinsic charge dynamics in passive capacitors, encoding matrix multiplication through spike amplitude and timing. This design addresses critical limitations such as weight drift, stochasticity, and power-intensive ADC bottlenecks. Key innovations include: amplitude-temporal dual encoding that enables constant-time analog dot-products; time-based decoding scheme that significantly reduces reliance on power-intensive ADCs; row-wise parallel architecture for concurrent dot-product calculations across multiple rows to enhance throughput; and value repetition exploitation in low-bit quantized vectors to reduce multiplications to constant time complexity. A PCB pro totype achieved a range-normalized RMSE of 1.80%—69.2% of the error in RRAM crossbar implementations—and a normalized error of 9.18%, corresponding to 77.1% of that in leading PCM crossbars. Implemented in a 40-nm CMOS technology, WireLightning macro delivers 465.47 TOPS/W at 4-bit precision, outperforming state-of-the-art analog accelerators while maintaining 0.23% range-normalized RMSE. By integrating algorithm-circuit co-design with physical computing, this work establishes capacitive computing as a promising path toward combining digital precision and analog efficiency in next-generation edge AI.

Although advances in event-based machine vision algorithms have demonstrated unparalleled capabilities in performing some of the most demanding tasks, their implementations under stringent real-time and power constraints in edge systems remain a major challenge. In this work, a reconfigurable hardware-software architecture called REMOT, which performs real-time event-based multi-object tracking on FPGAs, is presented. REMOT performs vision tasks by defining a set of actions over attention units (AUs). These actions allow AUs to track an object candidate autonomously by adjusting its region of attention and allow information gathered by each AU to be used for making algorithmic-level decisions. Taking advantage of this modular structure, algorithm-architecture codesign can be performed by implementing different parts of the algorithm in either hardware or software for different tradeoffs. Results show that REMOT can process 0.43–2.91 million events per second at 1.75–5.45 W. Compared with the software baseline, our implementation achieves up to 44 times higher throughput and 35.4 times higher power efficiency. Migrating the Merge operation to hardware further reduces the worst-case latency to be 95 times shorter than the software baseline. By varying the AU configuration and operation, a reduction of 0.59–0.77 mW per AU on the programmable logic has also been demonstrated.

In contrast to conventional vision sensors that produce images of the entire field-of-view at a fixed frame rate, dynamic vision sensors (DVS) are neuromorphic devices that only produce sparse events in response to changes in light intensity local to each pixel, making them promising technologies for use in demanding edge scenarios where energy-efficient intelligent computations are needed. While several early research have demonstrated promising results in performing high-level machine vision tasks using vision events only, these algorithms are often too complex for real-time deployments in edge systems with limited processing and storage capabilities. In this work, a novel hardware-software architecture, called REMOT, is proposed to leverage the unique properties of DVS to perform real-time multi-object tracking (MOT) on FPGAs. REMOT incorporates a parallel set of reconfigurable hardware attention units (AUs) that work in tandem with a modular attention-guided software framework running in the attached processor. Each hardware AU autonomously adjusts its region of attention by processing each vision event as they are produced by the DVS. Using information aggregated by the AUs, high-level analyses are performed in software. To demonstrate the flexibility and modularity of REMOT, a family of MOT algorithms with different hardware-software configurations and tradeoffs have been implemented on 2 different edge reconfigurable systems. Experimental results show that REMOT is capable of processing 0.43-2.22 million events per second at 1.75-5.68 watts, making them suitable for real-time operations while maintaining good MOT accuracy in our target datasets. When compared with a software-only implementation using the same edge platforms, our HW-SW implementation results in up to 33.6 times higher event processing throughput and 25.9 times higher power efficiency.