Demo Data from EDBT 2026 / reviewers in the wild / expert
Weian Deng
dblp:62/3795
· DBLP profile ↗
4ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 3 · 1 first-authorSystems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer graphics and multimedia
1 paper |
Image and video processing · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Image and video processing
edge detection |
0.0 | 1 | 1996 | A New Probabilistic Relaxation Scheme and Its Application to Edge Detection · IEEE Trans. Pattern Anal. Mach. Intell. 1996 |
Image and video processing
image segmentation |
0.0 | 1 | 1996 | A New Probabilistic Relaxation Scheme and Its Application to Edge Detection · IEEE Trans. Pattern Anal. Mach. Intell. 1996 |
Image and video processing › image segmentation
relaxation labeling |
0.0 | 1 | 1996 | A New Probabilistic Relaxation Scheme and Its Application to Edge Detection · IEEE Trans. Pattern Anal. Mach. Intell. 1996 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1996 | Hyperneural Network-An Efficient Model for Test Generation in Digital Circuits · IEEE Trans. Computers 1996 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1996 | Hyperneural Network-An Efficient Model for Test Generation in Digital Circuits · IEEE Trans. Computers 1996 |
Electronic design automation › hardware verification and test › VLSI testing
logic testing |
0.0 | 1 | 1996 | Hyperneural Network-An Efficient Model for Test Generation in Digital Circuits · IEEE Trans. Computers 1996 |
Methods — techniques the papers use, named apart from their topics
nonlinear update function · 0.0markov random field · 0.0hyperneural network · 0.0hopfield network · 0.0energy function optimization · 0.0bayes formula · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | A New Probabilistic Relaxation Scheme and Its Application to Edge DetectionabstractThis paper presents a new scheme for probabilistic relaxation labeling that consists of an update function and a dictionary construction method. The nonlinear update function is derived from Markov random field theory and Bayes' formula. The method combines evidence from neighboring label assignments and eliminates label ambiguity efficiently. This result is important for a variety of image processing tasks, such as image restoration, edge enhancement, edge detection, pixel classification, and image segmentation. The authors successfully applied this method to edge detection. The relaxation step of the proposed edge-detection algorithm greatly reduces noise effects, gets better edge localization such as line ends and corners, and plays a crucial role in refining edge outputs. The experiments show that our algorithm converges quickly and is robust in noisy environments. Weian Deng, S. Sitharama Iyengar |
IEEE Trans. Pattern Anal. Mach. Intell. | 1 |
| 1996 | Hyperneural Network-An Efficient Model for Test Generation in Digital CircuitsabstractThis paper considers the problem of applying neural network for logic circuit testing and proposes an efficient method based on hyperneural network (HNN). The HNN uses an energy function that not only considers binary relations but also captures all higher order relations among N neurons. We illustrate the hyperneural concept using two formulations. First, a constraint energy function is defined and the gate model is obtained. Second, the Hopfield network is reformulated to generate the gate level hyperneural model. The gate level HNN are used to give a mathematical form to the digital circuit that, in turn, requires optimization techniques to solve the test generation problem. We have used ISCAS'85 benchmark circuits to illustrate the method. Results are compared with those obtained from PODEM, MODEM, and FAN. Suresh Rai, Weian Deng |
IEEE Trans. Computers | 2 |
| 1995 | Tactical route planning: new algorithms for decomposing the mapabstractThe paper defines a new approach and investigates a fundamental problem in route planners. This capability is important for robotic vehicles (Martian Rovers, etc.) and for planning off road military manoeuvres. The emphasis throughout the paper is on the design and analysis and hierarchical implementation of our route planner. The work was motivated by anticipation of the need to search a grid of a trillion points for optimum routes. This cannot be done simply by scaling upward from the algorithms used to search a grid of 10,000 points. Algorithms sufficient for the small grid are totally inadequate for the large grid. Soon, the challenge will be to compute off road routes more then 100 km long and with a one or two meter grid. Previous efforts are reviewed and the data structures, decomposition methods and search algorithms are analyzed and limitations are discussed. A detailed discussion of a hierarchical implementation is provided and the experimental results are analyzed. The principal contributions of the paper are: new algorithms for decomposing the map and new search methods; analysis of new approaches; and the use of expert systems, deductive databases and mediators. Experimental results are included of a detailed implementation. John R. Benton, S. Sitharama Iyengar, Weian Deng, Nathan E. Brener, V. S. Subrahmanian |
ICTAI | 3 |
| 1995 | An efficient edge detection algorithm using relaxation labeling technique
S. Sitharama Iyengar, Weian Deng |
Pattern Recognit. | 2 |