The key characteristic of next generation embedded applications will be the intensive data transfer and storage and the need for efficient memory management. The embedded system designer community needs optimization methodologies and techniques, which do not change the input-output functionality of the software applications or the design of the underlying hardware platform. In this paper, the key focus is the efficient data access and memory storage of both dynamically and statically allocated data and their assignment on the data memory hierarchy of an MPSoC platform. We propose a design tool framework to efficiently automate the time-consuming optimizations for parallelization and memory mapping of static and dynamic data for MPSoCs.

Using software-controlled Scratch-Pad Memory (SPM) in Systems-on-Chip has the potential of reducing power consumption by using design-time application knowledge to reduce memory accesses and processor stalls. This paper presents a fully automatic application analysis and transformation tool which selects data-structures for transfer to the SPM and schedules data transfers between background memory and SPM (pre-fetching) to achieve both high performance and low power consumption. A case study applying this tool on an MPEG-4 video encoder shows an overall power reduction of 25%, a 40% power reduction in just the memories and a 40% reduction in processor cycles as compared to an optimized hardware-cache based solution.

A program transformation strategy is presented that is able to reduce the buffer size and power consumption for a relatively large class of (pseudo)regular data-dominated signal processing algorithms. Our methodology is targeted toward an implementation on programmable processors, but most of the principles remain valid for a custom processor implementation. As power and area cost are crucial in the context of embedded multimedia applications, this strategy can be very valuable. The feasibility of our approach is demonstrated on a representative high-speed video processing algorithm for which we obtain a substantial reduction of the area and power consumption compared to the classical approaches.

In this paper we present the second stage of a two-phase strategy for reducing the required background memory sizes for a large class of data-intensive multimedia applications. This strategy is particularly useful in an embedded application context, where memory size and the corresponding power consumption are the main cost factors together with data transfers. Our strategy optimizes the storage order of arrays in memory by trying to improve the reuse of memory locations, as well for elements of the same array as for elements of different arrays. Although size reduction is the main objective, an added benefit is a reduced power consumption due to the decreased capacitive load of the memories. The memory size reduction task is part of an overall memory size and power reduction methodology called ATOMIUM in which other tasks can increase its effectiveness (e.g. loop, transformations), but it can also be used on a stand-alone base. The effectiveness of our approach is demonstrated by experimental results for some real-life multimedia applications, for which a considerable memory size reduction was obtained.

In this paper, several DSP system design principles are presented which are valid for a large class of memory-intensive algorithms. Our main focus lies on the optimization of the memory and I/O, since these are dominant cost factors in the domain of video and imaging applications. This has resulted in several formalizable mapping principles, which allow to prevent the memory from becoming a bottleneck. First, it as shown that for this class of applications, compile-time data caching decisions not only have a large effect on the performance, but also can have an even larger effect on the overall system cost and power consumption. This is illustrated by means of experiments in which the whole range of no cache up to large cache sizes is scanned. Next, it is shown that when enforcing constant I/O rates to reduce buffer sizes, the area gain may be far more important than the small performance decrease associated with it. A technique to achieve this in an efficient way is proposed. The main test-vehicle which is used throughout the paper to demonstrate our approach is the class of motion estimation type algorithms.