With the rapid advancement in information technology, embedded systems have become integral to a wide range of critical applications. These systems often require continuous operation and cannot tolerate the downtime associated with traditional software updates, which typically necessitate a system reboot. To address this challenge, this paper proposes a novel hotpatching technique called Flexible Linked EXecution (FLEX) designed specifically for real-time embedded environments. FLEX enables seamless, dynamic firmware updates by redirecting all function calls and global variable accesses through a compile time generated Control Flow Table (CFT). In contrast to existing hotpatching approaches that depend on specialized hardware or impose strict limits on the number of patches and their size, FLEX is entirely hardware independent and supports scalable patching capacity bounded only by available flash memory and RAM. FLEX offers several unique features, including a relaxed consistency state synchronization mechanism to allow for gradual migration of program state, resolving all symbols at compile time into CFT indirections, applying updates via a double-buffered pointer swap to a new CFT, and a XIP compatible process that guarantees only a short, bounded pause time regardless of patch complexity. Experimental results show that FLEX maintains system stability and performance with an average execution overhead of about 11% and a predictable increase in flash memory usage of roughly 17%. These findings suggest that FLEX offers a robust and flexible solution for dynamically updating the software of embedded systems to ensure high availability and security without sacrificing performance.

Embedded systems rely on real-time operating systems (RTOS) for safety-critical applications, but the absence of fine-grained memory protection poses serious security risks. Existing protection mechanisms either require specialized hardware or rely on static configurations that fail to adapt to dynamic task behavior. This paper introduces Runtime Enforcement of Memory Access Protection (REMAP), which is a novel framework that combines LLVM-based static analysis with runtime Memory Protection Unit (MPU) reconfiguration to achieve fine-grained, dynamic compartmentalization for RTOS environments. REMAP constructs task-specific Access Control Table (ACT) at compile time and enforces them at runtime through on-demand MPU updates triggered by memory access violations. This lazy mapping strategy allows REMAP to support hundreds of compartments per task despite the limitation on the number of hardware MPU slots. Our prototype on ARMv8-M (Cortex-M33) demonstrates that REMAP enforces memory access control down to the function and variable level, protects shared buffers for secure Inter Process Communication (IPC), and prevents error propagation across tasks. Evaluation using the BEEBS benchmark suite shows that compartment merging significantly reduces fault frequency, yielding overheads under 5% across all benchmarks. Therefore, REMAP achieves precise, adaptive memory protection suitable for commercial RTOS deployments without compromising real-time performance.

CFDP and PFCD page allocation schemes are commonly adopted for datacenter SSDs. However, they have limitations on improving read performance as their fixed allocation unit of a single page causes the layout of related data to be dispersed. This paper proposes the Dynamic Clustering Page Allocation scheme, which dynamically adjusts the allocation unit by considering the characteristics of application-level I/Os to find an optimal trade-off between the utilization of channel-level parallelism and internal flash-chip features. Our simulation study shows that the DCPA scheme improves throughput for read-intensive applications compared to CFDP/PFCD by a factor of 1.59 – 3.15.

How do we infer a 3D scene from a single image in the presence of corruptions like rain, snow or fog? Straightforward domain randomization relies on knowing the family of corruptions ahead of time. Here, we propose a Bayesian approach—dubbed robust inverse graphics (RIG)—that relies on a strong scene prior and an uninformative uniform corruption prior, making it applicable to a wide range of corruptions. Given a single image, RIG performs posterior inference jointly over the scene and the corruption. We demonstrate this idea by training a neural radiance field (NeRF) scene prior and using a secondary NeRF to represent the corruptions over which we place an uninformative prior. RIG, trained only on clean data, outperforms depth estimators and alternative NeRF approaches that perform point estimation instead of full inference. The results hold for a number of scene prior architectures based on normalizing flows and diffusion models. For the latter, we develop reconstruction-guidance with auxiliary latents (ReGAL)—a diffusion conditioning algorithm that is applicable in the presence of auxiliary latent variables such as the corruption. RIG demonstrates how scene priors can be used beyond generation tasks.

The problem of inferring object shape from a single 2D image is underconstrained. Prior knowledge about what objects are plausible can help, but even given such prior knowledge there may still be uncertainty about the shapes of occluded parts of objects. Recently, conditional neural radiance field (NeRF) models have been developed that can learn to infer good point estimates of 3D models from single 2D images. The problem of inferring uncertainty estimates for these models has received less attention. In this work, we propose probabilistic NeRF (ProbNeRF), a model and inference strategy for learning probabilistic generative models of 3D objects’ shapes and appearances, and for doing posterior inference to recover those properties from 2D images. ProbNeRF is trained as a variational autoencoder, but at test time we use Hamiltonian Monte Carlo (HMC) for inference. Given one or a few 2D images of an object (which may be partially occluded), ProbNeRF is able not only to accurately model the parts it sees, but also to propose realistic and diverse hypotheses about the parts it does not see. We show that key to the success of ProbNeRF are (i) a deterministic rendering scheme, (ii) an annealed-HMC strategy, (iii) a hypernetwork-based decoder architecture, and (iv) doing inference over a full set of NeRF weights, rather than just a low-dimensional code. Videos and code are available at https://probnerf.github.io.

This paper proposes a new Flash Translation Layer (FTL) scheme that improves the performance of SSDs by minimizing resource contention. This is achieved by holistically managing all the FTL issues such as page allocation, garbage collection, wear leveling, and scheduling to maintain load balancing. The proposed ReCA-FTL consists of Resource Balancing Allocation, Erasure Counts Balancing Garbage Collection, Hot/Cold-Pool Balancing Wear Leveling, and Resource Contention Cost based Scheduling. The RBA, ECB GC, and H/C-PB WL schemes are designed to balance the number of free pages, erasure counts, recent erasure counts, and the hot/cold pool membership. The RCCS scheme reschedules jumbled incoming requests to utilize advanced flash-chip commands. This alleviates resource contention allowing SSDs to utilize all the resources more effectively. Our detailed simulation study shows that the proposed FTL scheme provides on average of 1.75 and maximum of 2.04 times higher throughput than a selected baseline for a variety of workloads.

This paper proposes the Cost-Age-Time Data Organized Garbage Collection (CATDOG) scheme, which clusters data based on their update frequencies to reduce the overhead of data migration. It also trades off between endurance and throughput, and efficiently erases multiple blocks to reduce garbage collection latency. To the best of our knowledge, this is the first paper to provide a holistic discussion on the effects of combining all three factors. Our simulation study shows that CATDOG achieves a maximum of 3.54 times higher throughput performance and 1.18 times greater endurance than a selected baseline for a heavy write workload.

The proliferation of Internet of Things (IoT) devices comes with many challenges among which security is one of the most serious issues. In order to address the security issue for low-end IoT devices, ARM recently proposed the platform security architecture (PSA), which provides execution isolation to safely manage and protect the computing resources of low-end IoT devices. However, developers implementing IoT services for PSA-based IoT devices need to follow complex development procedures and understand the PSA hardware, which dramatically increases the development time and cost of PSA-based IoT devices. This article analyzes vulnerabilities that may arise from general-purpose low-end IoT devices to derive the security requirements and essential security services for PSA-based IoT devices, and proposes a secure platform model based on the analysis results. The proposed secure platform model consists of System Security Services and Application Security Services based on the basic PSA model and essential trusted subsystems, and it is designed to be flexible and applicable to various types of PSA-based IoT devices. In addition, it provides secure platform services APIs to enable easy and fast development of IoT services. To evaluate the proposed secure platform model, two proof-of-concept implementations are provided by using both the basic PSA model with secure element (SE) and a reference device for ARM’s PSA. Finally, a case study shows that the development of IoT services can be done easily and quickly using the proposed security platform model.

Adaptive bitrate (ABR) streaming algorithms play an important role in ensuring a high Quality of Experience (QoE) for the consumer. However, a lot of ABR algorithms tend to be too ad hoc. In response, methods based on a Markov Decision Process (MDP) offer more intelligent models. In particular, Reinforcement Learning (RL) methods typically do so via QoE metrics. However, RL methods are plagued by high complexity and long convergence times due to their model-free nature. This paper proposes qMDP, which is an RL method with an MDP partially modeled by an M/D/1/K queue. Our study shows that qMDP results in higher QoE and faster convergence compared to a QoE-only model-free version.

The Flexible Dual TCP-UDP Streaming Protocol (FDSP) combines the reliability of TCP with the low latency characteristics of UDP. FDSP delivers the more critical parts of the video data via TCP and the rest via UDP. Bitstream Prioritization (BP) is a sliding scale that is used to determine the amount of TCP data that is to be sent. BP can be adjusted according to the level of network congestion. FDSP-based streaming achieves lower rebuffering time and less rebuffering instances than TCP-based streaming as well lower packet loss than UDP-based streaming. Our implementation and experiments on a real testbed shows that FDSP with BP delivers high quality, low-latency video, which is especially suitable for live video and subscription-based video.

Peer-to-peer streaming of HD video over ad-hoc 802.11 wireless networks is a popular application, but the received video quality, and therefore the user's Quality of Experience (QoE), depends heavily on the condition of the wireless channel used. This paper presents Active Scanning-based Dynamic Channel Switching (ASDCS), which ensures wireless video streaming takes place over the channel whose condition is most likely to provide good received video quality. ASDCS selects an initial channel before video streaming begins, assesses the performance of the current channel during streaming, and dynamically searches for a better channel if the current one is insufficient. Our simulation results show that ASDCS outperforms existing static queue-threshold and SINR-based methods.

Flexible Dual-TCP/UDP Streaming Protocol (FDSP) is a new method for streaming H.264-encoded HD video over wireless networks. The method takes advantage of the hierarchical structure of H.264/AVC syntax and uses TCP to transmit important syntax elements of H.264/AVC video and UDP to transmit less important elements. FDSP was shown to outperform pure-UDP streaming in visual quality and pure-TCP streaming in delay. In this work, FDSP is expanded to include a new parameter called Bitstream Prioritization (BP). The newly modified algorithm, FDSP-BP, is analyzed to measure the impact of BP on the quality of streaming for partially and fully congested networks. Our analysis shows that FDSP-BP is superior to pure-TCP streaming methods with respect to rebuffering instances, while still maintaining high visual quality.

Performance improvement of computer system I/O has been slower than CPU and memory technologies in terms of latency, bandwidth, and other factors. Based on this observation, how I/O is performed needs to be re-examined and explored for optimizations. To optimize the performance of computer system having multiple CPU cores and integrated memory controllers, we re-visits a CPU oriented I/O method where data movement is controlled directly by the CPU cores, instead of being indirectly handled by DMA engines using descriptors. This is achieved by leveraging the write-combining memory type and implementing the I/O interface as simple FIFOs. Our implementation and evaluation of the proposed method show that transmit latency and throughput significantly better for small and medium sized messages, and throughput for large messages is comparable to descriptor-based DMA approach.

Current I/O devices communicate based on the PCIe protocol, and by default, all the traffic passes through the CPU-memory complex. However, this approach causes bottleneck in system throughput, which increases latency and power as the CPU processes device specific protocols to move data between I/O devices. This paper examines the cost of this centralized I/O approach and proposes a new method to perform direct device-to-device I/O communication. Our proof-of-concept implementation using NetFPGA shows that latency can be reduced by more than 2×, CPU utilization can be reduced by up to 18%, and CPU power can be decreased by up to 31 W.

This paper proposes a novel cross-layer packet prioritization scheme that overcomes the limitations of conventional video prioritization schemes for IPTV system. In the conventional schemes, the Extend profile or frame unit is used for prioritization and these incur limited uses of the video prioritization schemes or unreliable transmission of the P-frame and B-frame headers. In order to overcome these limitations, the proposed scheme uses the MPEG-2 system information and the H.264/AVC NAL header information to prioritize the important video packets including the P-frame and B-frame headers. The experimental results using a testbed demonstrated that the proposed scheme has a significant performance enhancement over the conventional video prioritization schemes in terms of packet utilization ratio for video streaming, direct frame loss ratio, and PSNR.

Indoor positioning and tracking services are garnering more attention. Recently, several state-of-the-art localization techniques have been proposed that use radio maps or the sensors readily available on smartphones. This paper presents a localization system called Indoor Localization using Physical maps and smartphone Sensors (ILPS), which is based on a building blueprint database and smartphone sensors. The blueprint database and access points (APs) provide a number of reference points that can be used to acquire the initial position and adjust the user position each time a reference point is detected. The proposed method is implemented on a smartphone and tested in real indoor environments. The experiments with ILPS demonstrate that using a static blueprint will avoid the costly database updates that are usually required in other approaches due to signal attenuation. Furthermore, ILPS performs better than existing work in term of accuracy and effectiveness for indoor localization.

Although 3D video has become popular, streaming over wireless network faces a number of challenges. Due to frequent frame losses in wireless networks, temporal asynchrony occurs and results in serious visual fatigue for viewers. In order to provide better quality of 3D video, this paper proposes a new scheme called the Temporal Synchronization Scheme (TSS) for live 3D video streaming over wireless networks. TSS delivers video frames for the left and right views in the same frame order with the same transmission priority and compensates for frame damage and loss during the decoding phase. In addition, a new metric called the Stereoscopic Temporal Variation Index (STVI) is proposed to measure the degree of temporal asynchrony in 3D video. Subjective assessments demonstrate that STVI is an objective metric for measuring subjective quality. Moreover, our study shows that the proposed scheme results in better 3D video quality than the conventional method in terms of STVI and MOS.

Many challenges and limitations stand in the way of streaming high resolution video content over a wireless network. A shift towards the 60-GHz band is taking place in order to accommodate for current High Definition streaming demands. However, today's Wi-Fi networks are able to provide the necessary bandwidth with the help of compression. In this paper we evaluate the effectiveness of streaming video over wireless LANs using the H.264 codec. Our study shows that streaming HD content wirelessly over 802.11n is a viable option. However, perceptual quality of video is affected by the amount of background traffic and the presence of interfering nodes, i.e., hidden nodes.

Although many techniques have been proposed to improve text input on touch screens, the vast majority of this research ignores non-alphanumeric input (i.e., punctuation, symbols, and modifiers). To support this input, widely adopted commercial touch-screen interfaces require mode switches to alternate keyboard layouts for most punctuation and symbols. Our approach is to augment existing ten-finger QWERTY keyboards with multi-touch gestural input that can exist as a complement to the moded-keyboard approach. To inform our design, we conducted a study to elicit user-defined gestures from 20 participants. The final gesture set includes both multi-touch and single-touch gestures for commonly used non-alphanumeric text input. We implemented and conducted a preliminary evaluation of a touch-screen keyboard augmented with this technique. Findings show that using gestures for non-alphanumeric input is no slower than using keys, and that users strongly prefer gestures to a moded-keyboard interface.

Although the latest video codecs such as H.264/AVC, H.264/SVC, and VP8 were developed with network-friendly features, provisioning the quality of video delivery over IEEE 802.11 wireless networks is still challenging because of error-prone medium and random access. This paper evaluates the quality of video delivery using those latest video codecs over IEEE 802.11. Our results show that reduction of coded video data, consideration of the queue size of each Access Category, and the mandatory implementation of error recovery features in H.264/SVC can help provide robust multimedia transmission over IEEE 802.11. In addition, the performance of the latest video codecs is compared via extensive simulation scenarios. Our comparison shows that VP8 achieves good video quality with the basic medium access control techniques of IEEE 802.11, whereas H.264/AVC and H.264/SVC benefit significantly from appropriate mapping schemes between encoded video fragments and IEEE 802.11e Access Categories.

More and more mobile devices, such as smartphones and pad/tab devices, are being used in IEEE 802.11 Wireless LANs (or Wi-Fi). However, mobile users are currently unsatisfied with using Wi-Fi on the move due to large handoff delay. In order to perform fast handoff, this paper proposes a new scheme using a geomagnetic sensor (or a digital compass) embedded in mobile devices. The proposed scheme predicts the direction of movement of a Mobile Station (MS) from the currently associated Access Point (AP) and performs active scanning with a reduced number of channels. The proposed scheme was implemented in Android smartphones and their performance was evaluated in a real indoor WLAN environment. Our test results show that the proposed scheme reduces handoff delay compared to conventional handoff and selective scanning scheme. In addition, the proposed scheme does not require modification to existing APs, which makes it very practical for using real-time multimedia services on current mobile devices.

Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscalar processors. One promising method of exploiting TLP is dynamic speculative multithreading (D-SpMT), which extracts multiple threads from a sequential program without compiler support or instruction set extensions. This paper introduces Cascadia, a D-SpMT multicore architecture that provides multigrain thread-level support and is used to evaluate the performance of several benchmarks. Cascadia applies a unique sustainable IPC (sIPC) metric on a comprehensive loop tree to select the best performing nested loop level to multithread. This paper also discusses the relationships that loops have on one another, in particular, how loop nesting levels can be extended through procedures. In addition, a detailed study is provided on the effects that thread granularity and interthread dependencies have on the entire system.

This paper proposes a technique called Global Path-Cache (GPC) that provides fast handoffs in WLANs. GPC maintains a history of mobile stations' mobility patterns in a network to assist in the prediction of the next point-of-attachment. GPC properly captures the dynamic behavior of the network and mobile stations, and provides accurate next AP predictions. Our simulation study shows that GPC virtually eliminates the need to scan for APs during handoffs and results in much better overall handoff delay compared to existing methods.

While most previous studies on mobile ad hoc networks (MANETs) rely on the assumption that nodes are randomly distributed in the network coverage area, this assumption is unlikely to hold, as nodes tend to be cluttered around hot spots like the site of an accident or disaster. We refer to this as a clustered layout. Intuitively, a MANET with the clustered layout may suffer from serious performance degradation due to the excessive collisions in congested hot spots and space underutilization of sparse areas. In this paper, we propose a power-controlled network protocol, called the power-stepped protocol (PSP), that maximizes the spatial utilization of limited channel bandwidth. Using a number of discrete power levels available for the underlying wireless network hardware, PSP finds the appropriate power level for each node in a distributed and a coordinated manner without causing any serious problem at the medium access control and network routing layers. A unique feature of this approach is the use the chosen radio power for both data and control packets, and thus, it requires neither any special mechanism (e.g., a separate control channel) nor frequent power adjustments. Our extensive ns-2-based simulation results have shown the proposed PSP provides excellent performance in terms of packet delivery ratio and delay, as well as the network capacity.

Due to its topological generality and flexibility, the k-ary n-cube architecture has been actively researched for various applications. However, the processor allocation problem has not been adequately addressed for the k-ary n-cube architecture, even though it has been studied extensively for hypercubes and meshes. The earlier k-ary n-cube allocation schemes based on conventional slice partitioning suffer from internal fragmentation of processors. In contrast, algorithms based on job-based partitioning alleviate the fragmentation problem but require higher time complexity. This paper proposes a new allocation scheme based on isomorphic partitioning, where the processor space is partitioned into higher dimensional isomorphic subcubes. The proposed scheme minimizes the fragmentation problem and is general in the sense that any size request can be supported and the host architecture need not be isomorphic. Extensive simulation study reveals that the proposed scheme significantly outperforms earlier schemes in terms of mean response time for practical size k-ary and n-cube architectures. The simulation results also show that reduction of external fragmentation is more substantial than internal fragmentation with the proposed scheme.

Abstract Although establishing correct and efficient routes is an important design issue in mobile ad hoc networks (MANETs), a more challenging goal is to provide energy efficient routes because mobile nodes' operation time is the most critical limiting factor. This article surveys and classifies the energy‐aware routing protocols proposed for MANETs. They minimize either theactive communication energyrequired to transmit or receive packets or theinactive energyconsumed when a mobile node stays idle but listens to the wireless medium for any possible communication requests from other nodes.Transmission power control approachandload distribution approachbelong to the former category, andsleep/power‐down mode approachbelongs to the latter category. While it is not clear whether any particular algorithm or a class of algorithms is the best for all scenarios, each protocol has definite advantages/disadvantages and is well suited for certain situations. The purpose of this paper is to facilitate the research efforts in combining the existing solutions to offer a more energy efficient routing mechanism. Copyright © 2003 John Wiley & Sons, Ltd.

This paper presents Linux/SimOS, a Linux operating system port to SimOS, which is a complete machine simulator from Stanford. The motivation for Linux/SimOS is to alleviate the limitations of SimOS, which only supports proprietary operating systems. The contributions made in this paper are two-fold: First, the major modifications that were necessary to run Linux on SimOS are described. Second, a detailed analysis of the UDP/IP protocol and M-VIA is performed to demonstrate the capabilities of Linux/SimOS. The simulation study shows that Linux/SimOS is capable of capturing all aspects of communication performance, including the effects of the kernel, device drivers, and network interface.

This paper reevaluates the multicast protocols for MANETs in terms of energy efficiency and proposes a new robust multicast protocol, called two-tree multicast (TTM). Multicast protocols can be broadly categorized into two types, tree-based multicast and mesh-based multicast, based on the network structure along which multicast packets are delivered to multiple receivers. Mesh-based protocols are more robust to mobility and result in high packet delivery ratio. On the other hand, multicast trees are more energy efficient than multicast meshes. This is because mesh-based protocols depend on broadcast flooding within the mesh and therefore, mobile nodes in the mesh must receive all multicast packets during the multicast communication. The proposed TTM uses two trees, a primary and an alternative backup tree, to improve energy efficiency compared to the mesh-based protocols and to offer a better energy balance and packet delivery ratio than the free-based protocols. Performance evaluation study shows that the proposed TTM saves energy consumption by a factor of 1.9/spl sim/4.0 compared to the mesh-based multicast. In terms of combined performance metric, energy per delivered packet, TTM shows up to 80% and 40% improved performance than the mesh-based multicast and the conventional shared tree multicast, respectively.

Mapping virtual process topology to physical processor topology is one of the most important issues in parallel computing. The mapping problem for switch-based cluster systems of irregular topology is very complicated due to the connection irregularity and routing complexity. This paper proposes two mapping schemes for irregular cluster systems, which try to map the nearest neighbors in the process topology to physically adjacent processors. In addition, an application-oriented performance metric, weighted cardinality, is introduced to represent the quality of mapping. A simulation study shows that, for a virtual topology of a 16/spl times/16 mesh, the proposed mapping schemes result in better mapping quality and about 15/spl sim/20% shorter communication latency compared to random mapping. The proposed algorithms should also be beneficial when they are applied to metacomputing and cluster of cluster systems, where the communication costs are an order of magnitude different depending on the relative position of the processor nodes.

This paper proposes a Barrier Tree for Meshes (BTM) to minimize the barrier synchronization latency for two-dimensional (2D) meshes. The proposed BTM scheme has two distinguishing features. First, the synchronization tree is 4-ary. The synchronization latency of the BTM scheme is asymptotically /spl theta/(log/sub 4/ n), while that of the fastest scheme reported in the literature is bounded between /spl Omega/(log/sub 3/ n) and /spl theta/(n/sup 1/2/), where n is the number of member nodes. Second, nonmember nodes are neither involved in the construction of a BTM nor actively participate in the synchronization operations, which avoids interference among different process groups during synchronization. This not only results in low setup overhead, but also reduces the synchronization latency. The low setup overhead is particularly effective for the dynamic process model provided in MPI-2. Extensive simulation study shows that, for up to 64/spl times/64 meshes, the BTM scheme results in about 40/spl sim/70 percent shorter synchronization latency and is more scalable than conventional schemes.

A method for testing multi-protocol implementation under test (IUT) with a single test suite has been proposed in the literature. It tests a multi-protocol IUT in an integrated way compared to the conventional method, where a single-layer test method and a single-layer embedded test method are applied, respectively, to the upper layer protocol and to lower layer protocols. However, it did not consider how to generate the test cases automatically but proposed only an approach for the test method. This paper proposes an algorithm called multi-protocol test method (MPTM) for automatic test case generation based on that approach. With the MPTM, a multi-protocol IUT consisting of two protocol layers is modeled as two finite state machines (FSMs), and the relationships between the their transitions are defined as a set of transition relationships, pre-execution and carried-by. The proposed algorithm is implemented and applied to a simplified TCP/IP and B-ISDN signaling/SSCOP (service specific connection-oriented protocol). The MPTM is able to test the multi-protocol IUT even though the interfaces between the protocol layers are not exposed. It also allows the same test coverage as conventional test methods, but with a much smaller number of test cases and operations.

As the performance gap between processor and memory grows, memory latency becomes a major bottleneck in achieving high processor utilization. Multithreading has emerged as one of the most promising and exciting techniques used to tolerate memory latency by exploiting thread-level parallelism. The question, however, remains as to how effective multithreading is on tolerating memory latency. The performance of multithreading is not only affected by the overlapping of memory latency with useful computation, but also strongly depends on the cache behavior and the overhead of multithreading (e.g., thread management and context-switch costs). In particular, multithreading affects the behavior of caches, and, thus, the overall performance in a nontrivial fashion. To study these issues, this paper presents the Multithreaded Virtual Processor (MVP) model. MVP integrates the multithreaded programming paradigm and a modern superscalar processor with support for fast context switching and thread scheduling. Our studies with MVP show that, in general, the performance improvements are obtained not only by tolerating memory latency but also lower cache miss rates due to exploitation of data locality. However, multithreading creates an additional stress on the memory hierarchy caused by the interference among threads. Also, the dynamic behavior of multithreaded execution hinders the instruction locality that results in a high number of misses in the L1 instruction cache.

The asynchronous nature of the dataflow model of computation allows the exploitation of maximum inherent parallelism in many application programs. However, before the dataflow model of computation can become a viable alternative to the control flow model of computation, one has to find practical solutions to some problems such as efficient handling of data structures. The paper introduces a new model for handling data structures in a dataflow environment. The proposed model combines constant time access capabilities of vectors as well as the flexibility inherent in the concept of pointers. This allows a careful balance between copying and sharing to optimize the storage and processing overhead incurred during the operations on data structures. The mode) is compared by simulation to other data structure models proposed in the literature, and the results are good.>