In repeat-pass interferometric synthetic aperture radar (In-SAR), the coherence loss derived from temporal decorrelation can be modeled using an exponential decay function. Many researches have investigated the relationships between decay parameters over various land-cover types for C-band SAR satellites. Although ALOS PALSAR provides many L-band SAR images, its revisit time was insufficient for understanding the rapid exponential drop in temporal decorrelation. Due to the lack of an appropriate archived dataset, analyzing the decay parameters for L-band SAR was a challenging task. In this study, we processed four-year interferometric pairs derived from ALOS-2 PALSAR-2 full-aperture ScanSAR images. This dataset has a 14 day minimum temporal interval. We selected Nairobi, Kenya, in the middle of the East African rift, as the study area and investigated how decay functions differ over multiple land-cover types. In addition, we compared decay models for Sentinel-1 interferograms. This study demonstrates that the decay parameters of L-band coherence completely differs across forest types, whereas C-band coherence is low coherence regardless of forest type.

Article Free Access Share on 300MHz design methodology of VU for emotion synthesis Authors: Takayuki Kamei System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Hideaki Takeda System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Yukio Ootaguro System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Takayoshi Shimazawa System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Kazuhiko Tachibana System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Shin'ichi Kawakami Information System Dept., TOSHIBA Microelectoronics Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan Information System Dept., TOSHIBA Microelectoronics Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Seiji Norimatsu EDA and DFT Grp. Micro & Custom LSI Design Dept., Micro & Custom LSI Div., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan EDA and DFT Grp. Micro & Custom LSI Design Dept., Micro & Custom LSI Div., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Fujio Ishihara System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Toshinori Sato System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Hiroaki Murakami System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Nobuhiro Ide System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Yukio Endo System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Akira Aono System LSI development Grp., Toshiba Microelectoronics Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System LSI development Grp., Toshiba Microelectoronics Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile , Atsushi Kunimatsu System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., TOSHIBA Corp., 580-1, Horikawa-cho, Saiwaiku, Kawasaki 210-8520, JapanView Profile Authors Info & Claims ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation ConferenceJanuary 2000 Pages 635–640https://doi.org/10.1145/368434.368847Published:28 January 2000Publication History 4citation178DownloadsMetricsTotal Citations4Total Downloads178Last 12 Months16Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A single-board 14.3-MOPS (million operations per second) video signal processor module (VSPM) has been developed. The module is fully microprogrammable and processes up to a 128 pel*128 pel subimage every 16.7 ms. Using a number of homogeneous VSPMs aligned in parallel, a real-time video signal processing environment is provided on the basis of an overlap-save or overlap-add technique. An experimental system has been constructed in order to demonstrate the signal processor approach's effectiveness for video signals by implementing picture coding algorithms. Due to software control capability, various kinds of picture coding techniques can be evaluated by the system.>

Two important functional LSIs for the realtime Video Signal Processor (VSP) have been developed. One is the Pipelined Arithmetic Unit (PAU) and the other is the Address Generation Unit (AGU). The PAU chip employs a flexible pipelined architecture optimized for L1 or L2-norm distance calculation, used in a wide variety of image processing. The AGU chip, including 15-word register file for pointer alteration, offers a user-friendly two dimensional pointer addressing. A realtime Video Signal Processor Module (VSPM), composed of one PAU, four AGUs and memories, has been implemented for multiprocessor VSP configuration. Thanks to software control capability, various kinds of picture coding techniques can be evaluated by the system.