This work presents an ultra-low-power, single-ended successive approximation register (SAR) analog-to-digital converter (ADC) designed explicitly to digitize sensor data. Due to the single-ended nature of the sensor’s output data, very efficient designs for differential SAR ADCs cannot be utilized. Hence, a monotonic capacitor switching procedure for single-ended inputs has been developed and is introduced in this paper. Re-charging of capacitances during the SAR algorithm is no longer required, resulting in significant energy savings compared to conventional approaches.The SAR ADC is implemented in a 22nm CMOS FDSOI technology. It achieves a measured signal-to-noise and distortion ratio (SNDR) of 49.1dB and a spurious-free-dynamic-range (SFDR) of 61dB. It draws a simulated 1.2μW yielding a Walden figure of merit (FoMW) of 50.2fJ/conversion step at a sampling rate of 100kS/s. The circuit occupies an area excluding pads of only 275 x 220μm2.

This article presents an area- and power-efficient transmission/receiving (TX/RX)-isolation switch implemented in a 3072-ch ultrasound (US) in-probe 2-D array transceiver application-specific integrated circuit (ASIC) for real-time 3-D imaging. Conventional T/R switches that protect low voltage (LV) receivers from high voltage (HV) bipolar pulses require at least four HV-MOSFETs. The proposed dynamic gate–source shunt topology, which utilizes a negative-HV-transmit-driven shunt switch, eliminates area- and power-hungry HV-level shifters and ensures the OFF state of our T/R switch for HV/LV isolation during TX periods. In addition, source-driven HV-PMOS for ON/OFF control enables both gate charging and discharging using a single HV-PMOS. Thus, our T/R switch enables implementation with only three HV-MOSFETs for the first time in the world. The HV-level-shifter-less architecture also enables static-power-free operation in TX periods and consumption of only$12.1~\mu \text{W}$in RX periods. Further, sequential input impedance control suppresses switching noise, which causes unwanted sound transmitted during TX to RX switching, by −18.1 dB. Moreover, by preparing an attenuation mode, a per-channel TX to RX self-loopback test can be performed. This function provides an on-wafer ac test without probing 3072 electrodes and it can be applied to the field diagnosis of assembled US probes.

This article presents a fully integrated charge pump with optimized gate voltages for energy harvesting applications. In this article, design tradeoffs of gate voltages in low input voltage capacitive dc–dc converter designs are discussed and analyzed. The analysis shows that these tradeoffs can result in an optimum point where power losses can be minimized. Hence, gate voltage optimization is proposed to improve the power conversion efficiency. To prove the concept, five- and three-stage charge pumps with optimized gate voltages are implemented with the 180-nm CMOS technique. Down to 0.12-/0.13-V startup voltages are achieved by the proposed five-/three-stages design correspondingly. Comparing it with a similar three-stage linear charge pump in previous state-of-the-art research, a 20% peak power conversion efficiency improvement is achieved by the proposed design under the same 0.18-V input voltage.

This paper presents a gate voltage optimized fully integrated charge pump for thermoelectric energy harvesting applications. In this paper, the trade-off generated by rising the gate voltage of switching transistors are discussed. The proposed 5/3-stage design, which implemented with 180 nm CMOS technique, achieved a down to 0.12V/0.13V startup voltage correspondingly with the proposed technique. A 20% peak power conversion efficiency improvement is achieved when comparing with a similar 3-stage linear charge pump in previous state-of-the-art research.

This work presents a novel control loop concept to adjust dynamically a differential ring oscillators (DRO) biasing in order to improve the phase noise performance (PN) in the ultra-low-power domain. Applying this proposed feedback system on any DRO with a tail current source is possible. The following paper presents the proposed concept and includes measurements of a 180 nm CMOS integrated prototype system, which underlines the feasibility of the discussed idea. Measurements show an up to 35 dBc/Hz phase noise improvement with an active control loop. Moreover, the tuning range of the implemented ring oscillator is extended by about 430 % compared to fixed bias operation. These values are measured at a minimum oscillation power consumption of 55 pW/Hz.

This paper presents a wide-dynamic-range high-resolution time-domain converter concept tailored for low-power sensor interfaces. The unique system structure applies different techniques to reduce circuit complexity, power consumption, and noise sensitivity. A multi-cycle concept allows a virtual delay line extension and is applied to achieve high resolution down to 1ns. At the same time, it expands the dynamic range drastically up to 2.35 ms. Moreover, individually tunable delay elements in the range of 1ns to 12 ns allow on-demand flexible operation in a low- or high-resolution mode for smart sensing applications and flexible power control. The concept of this paper is evaluated by a custom-designed FPGA supported PCB. The presented concept is highly suitable for on-chip integration.

A Time-Domain Resistance-to-Digital Converter (RDC) with a referential 1-bit ΔΣ Modulated variable resistor is proposed. The proposed RDC converts an input resistance to a frequency and compares a referential variable resistor to decrease a sensor read-out error caused by a non-linearity of an oscillation frequency. A 1-bit ΔΣ modulated variable resistor is demodulated by an oscillator and a counter. Hence a low-pass filter circuit is not required. In addition, non-linearity canceling feedback is proposed to decrease comparison time. This prototype RDC achieves 10.1bits conductance resolution at 1kSps in 10μS to 110μS full-scale range.

This paper presents a fully integrated charge pump with gate voltage optimization for energy harvesting applications. In this paper, the benefits of powering a multistage charge pump with its own output are analyzed and the optimization of gate voltage are discussed. With optimized gate voltages, a 5-stage and a 3-stage charge pump are implemented with 180nm CMOS technique. Down to 0.12V/0.13V startup voltages are achieved by the proposed 5/3-stage design correspondingly. Comparing with a similar 3-stage linear charge pump in previous state-of-the-art research, a 20% peak power conversion efficiency improvement is achieved by the proposed design under the same 0.18 V input voltage.

This paper presents a coin-cell powered small size wireless sensor node with a sensor bridge biased by an energy-efficient DC-DC converter. To reduce the switching noise of the DC-DC converter, a Wheatstone bridge with differentially balanced in wide resistance range is used. Circuit parameters, such as bridge resistances and amplifier offset are automatically set to the optimal values in the startup sequence. Proposed sensor interface achieved power reduction by 57.3% and intermittent operation further reduces the power consumption by 78.6% from which uses LDO. The developed tiny wireless sensor node with a nanoscale gas sensor device successfully demonstrated 100ppm hydrogen gas detection.

In this paper, a noble gas sensing system using a large scale integrated resistive sensor array and its interface system is introduced. Accuracy improvement, compared to conventional techniques, was achieved using our proposed opamp output impedance calibration technique. This technique makes it possible to use a low power, weak drivability opamp in the interface circuit. This paper shows the calibration method which reduces the sneak path current error from 83.6% to 1.2% through MATLAB simulations. A prototype system with 1,024 gas sensors integrated in one chip, discrete ICs of opamp, ADCs, and an FPGA was developed, and the effectiveness of the system is demonstrated.

To realize high-resolution pipelined and pipelinedSAR analog-to-digital-converters (ADCs), an accurate residue amplifier is necessary. However, realizing such an amplifier in scaled CMOS is challenging due to the worsened transistor characteristics. Prior works focused on gain calibration techniques to mitigate the use of low-gain amplifiers, in return of system complexity and prolonged startups. In this paper, we introduce a digital amplifier (DA) technique to realize powerefficient and accurate amplification in scaled CMOS. DA cancels out all errors (i.e., gain error, nonlinearity, incomplete settling, power supply noise, and thermal noise) of the low-gain amplifier by feedback based on successive approximation. The DA accuracy can be arbitrary set by configuring the number of bits in the DA capacitor digital-to-analog-converter; the amplifier gain is decoupled from the transistor intrinsic gain which is suitable for scaled CMOS integration. We also show that the power efficiency can be enhanced over conventional opamp-based designs with relaxed settling error requirements of DA-based multiplying digitalto-analog-converters (MDACs). Moreover, the circuit design of DA-based MDACs is further discussed. Measurement results of the calibration-free 0.7-V 12-bit 160-MS/s pipelined-SAR ADC implemented in 28-nm CMOS are reported. Without calibration, the ADC achieves signal-to-noise-and-distortion-ratio = 61.1 dB, figure-of-merit = 12.8 fJ/conv., which is over 3× improvement compared with conventional calibration-free high-speed pipelined ADCs. In addition, we evaluate the DA's process scalability by comparing the measured results of the DA-based MDAC prototyped in 65and 28-nm CMOS. We observe 2×-3× improvement in speed, power, and area mainly resulting from the DA's process scalability.

This paper presents an ADC with re-configurability between SAR-only mode and delta-sigma (ΔΣ assisted mode). The ΔΣ assisted mode brings resolution enhancement. Proposed ADC shares a capacitor array for SAR, feedback DAC, and integrator capacitor in ΔΣ loop, which can reduce the circuit size. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at 32 MS/s and power consumption of 0.55 mW. The SNDR is improved to 62.9 dB by ΔΣ assisted mode.

This paper presents a low power DT sigma-delta modulator for wide variety of sensor application using a ring amplifier for SC-integrator. The topology is a second order modulator with single-bit quantizer. Dead-zone effect of the ring amplifier in oversampling ADC is discussed. The fabricated test chip in 65nm CMOS process achieved SNDR of 62dB and 1MHz signal band at sampling frequency of 102.4MHz. The power consumption is 1mW and FoM is 483fJ/conv.step.

A single-inductor dual-output wireless power delivery system for small size battery-less NAND flash memory card is presented. The power delivery system uses two rectifiers connected to a single inductor which is synchronously switched by pseudo-random-sequence PWM signal with induced AC voltage. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 % and maximum total transmitting power of 0.5 W. The test chips were designed and fabricated using 0.18um-CMOS with high-voltage LDMOS option.

A 0.3-0.8 V low-power 2-bit/step asynchronous successive approximation register analog-to-digital converter (ADC) is presented. A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. Simple digital calibration is enabled by generating the reference internally. The prototype ADC fabricated in a 40 nm CMOS achieved a 44.3 dB signal-to-noise-plus-distortion ratio (SNDR) with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 4.8 fJ/conv-step at 0.4 V and operates down to 0.3 V.

An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm2and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.

A reduced-reflection multi-drop bus system using Dicode (1-D) partial response signaling transceiver is presented for the first time in the world. Directional couplers on transmission lines arranged with equi-energy distributing and exact impedance matched conditions allow the bus to reach to 12.5Gbps/link speed, which is the world's fastest data link speed with multi-drop bus architecture. Dicode partial-response signaling method with a half-rate architecture was used where a precoder is placed in the transmitter to make the signal best fit for the channel to eliminate inter symbol interference (ISI).

An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcmbiased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.

This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2.

A 2nd order discrete time (DT) ΔΣ modulator with very wide supply voltage range of 0.25–1.8 V is presented. An inverter-opamp self-configuring amplifier (IOSA) is proposed with sufficient gain through sub-threshold to strong inversion region. The amplifier senses the supply voltage and automatically configures either to operate as an inverter or an opamp. The prototype ADC fabricated in 180nm CMOS achieved SNDR of 53dB at a supply voltage of 0.3V and a best FoM of 0.09 pJ/step. At 1.8 V supply the modulator achieves SNDR 61dB and operates down to 0.25V.

This paper presents a low-power inductive-coupling link in 90-nm CMOS. Our newly proposed transmitter circuit uses a charge-recycling technique for power-aware 3-D system integration. The cross-type daisy chain enables charge recycling and achieves power reduction without sacrificing communication performance such as a high timing margin, low bit error rate and high bandwidth. There are two design issues in the cross-type daisy chain: pulse amplitude reduction and another is inter-channel skew. To compensate for these issues, an inductor design and a replica circuit are proposed and investigated. Test chips were designed and fabricated in 90-nm CMOS to verify the validity of the proposed transmitter. Measurements revealed that the proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading the timing margin, data rate, or bit error rate. In order to investigate the compatibility of the transmitter with technology scaling, a simulation of each technology node was performed. The simulation results indicate that the energy dissipation can be potentially reduced to less than 10 fJ/bit in 22 nm CMOS with proposed cross-type daisy chain.

In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18-$\mu$m mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450$\mu$m, with 6.9 mW of power. The phase noise was measured to be$-$79.06 dBc/Hz at a 100 kHz offset,$-$101.66 dBc/Hz at a 1 MHz offset, and$-$107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated.

This paper discusses analysis and techniques for mitigating interference of an inductive-coupling inter-chip link. Electromagnetic interference from power/signal lines and to SRAM circuits was simulated and measured. In order to verify the interference, test chips were designed and fabricated using 65-nm CMOS technology. The measurement results revealed that: 1) interference from power lines depends on the shape of the power lines; 2) interference from signal lines can be canceled by increasing transmitter power by only 9%; and 3) interference with SRAM circuits is less important than other issues under ordinary conditions. Based on the measurement results, interference mitigation techniques are proposed and investigated.

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.

A 480Mb/s wireless real-time bus trace system with a pulse-based inductive coupling channel array was developed using a 0.25μm CMOS digital process. The size and pitch of the inductor array are determined by numerical calculation to optimize the tradeoff between the channel coupling, crosstalk, and alignment tolerance. A low-power quasi-synchronous system is proposed to obtain an enough timing margin for RX pulse detection under the presence of the clock skew.