An all-in-one anomaly-detection processor for an extensive range of industrial applications is presented. This processor uniquely integrates A/D converters as a multiple-sensor interface, a generator of pseudo images and a DNN accelerator for image recognition on a single 7nm CMOS chip. The chip can process not only images but also any sensor signals with enhanced sensor-fusion capability. It operates with only 150mW power at 100MHz under a supply voltage of 0.75V, including the 16-channel A/D converters. The effectiveness of this single-chip anomaly-detection processor is proved with two actual industrial applications. To the best of the authors’ knowledge, this is the first integration of digital AI and high-performance A/D converters with a FinFET CMOS technology.

In this paper, we present ongoing research on a method for human pose estimation under varying lighting conditions, with enhanced occlusion handling, real-time efficiency, and improved association accuracy. Our approach addresses a significant limitation of conventional pose estimation methods, which typically treat the tasks of keypoints localization and body joint association separately. By integrating these tasks through transformer-based architectures, we simultaneously localize and associate keypoints, leading to superior performance in complex environments. Features are encoded and decoded within this framework, showing considerable improvements in managing occlusions. This research is in its preliminary stages, and we are continuing to refine and enhance the method, with plans to publish further results in the future.1

Digital technologies are rapidly prevailing in our society, and there the performance of analog circuits is progressing and their market amount is growing steadily. We have experienced that in many cases analog parts may be small compared to digital ones, but analog ones are troublesome. Testing of analog circuits plays a crucial role in achieving both reliability and low cost such as in computer, Internet, AI, IoT and automotive systems. Also, in ATE systems, analog parts are key. Analog testing is a challenge including circuit design, signal processing algorithms and measurement methods/systems.This session will discuss analog testing related issues with three talks by researchers from industry. The first talk introduces a state-of-art low jitter 1GHz crystal oscillator by an ATE manufacturer. The second one explains a time measurement BOST using a successive approximation register time-to-digital converter (SAR TDC) with fine resolution by a semiconductor company. The third one is a proposal of an ADC diagnosis method using obtained self-calibration parameters, by an ADC design researcher.

We have developed a code compiler to compress unstructurally pruned DNN models and demonstrated inference time less than 1 msec with AUC accuracy over 90 % for an anomaly detection task using MVTec AD dataset and edge Graphics Processing Unit (GPU) devices. Reduced RepVGG convolutional neural network (CNN) architecture is applied to an explainable deep one-class classification (XDOC) algorithm and such fast inference is obtained without sacrificing the accuracy by using a training scheme, CutPaste, to keep the accuracy high under an extremely higher pruning rate condition.

An FPGA-based accelerator for the iterative-closest-point (ICP) algorithm has been proposed, which achieves 4.8-times-faster object-pose estimation by a picking robot compared with the state-of-the-art technique. Experiments of the proposed FPGA-based ICP accelerator using Amazon Picking Contest data sets have confirmed that the object-pose estimation by the ICP takes only 0.6 seconds, and the entire picking process takes 2.0 seconds with power consumption of 6.0 W.

A 17-MS/s 52.5-dB-SNDR 4.7-mW 0.045-mm2cyclic ADC has been achieved by the low-cost 0.18-μm CMOS. The only-26-dB gain of a simple op-amp has been successfully compensated by the proposed gain-assisted MDAC circuit and by the novel simple attenuation-based digital calibration. The prototype ADC chip has achieved the fastest speed, the smallest size and the best FOM among the high-speed (> 5 MS/s) highresolution (SNDR > 50 dB) low-cost-CMOS cyclic ADCs.

A 1-GS/s 11.5-ENOB (71.2-dB-SNDR) time-interleaved analog-to-digital converter with fully digital background calibration was demonstrated. To generate multi-phased sampling clocks with low noise and low power, passive delay circuits with a differential-clock-sharing structure are proposed. A double filter for reducing sub-ADC kickback combined with bandwidth-mismatch calibration is also proposed. The proposed techniques are essential to assure accurate sampling. This is considered to be the first giga-sampling-rate ADC with over-70-dB SNDR and over-80-dB SFDR.

A novel nonlinear foreground calibration of pipeline A/D converters based on LMS algorithm has been proposed and verified by macro-based simulation as well as measurement of test chip. The prototype 23-mW 50-MS/s 10-bit pipeline ADC in 0.13-mum CMOS has confirmed that the proposed calibration can accurately and rapidly correct the inaccuracy caused both by heavy nonlinearity of low-gain op-amps and by their incomplete settling without requiring any dedicated voltage references, complicated structures or timing sequence and hence can be used for various applications.