This paper studies noise-predictive maximum-likelihood (NPML) detection in the case where noise prediction is accomplished by infinite, rather than finite, impulse-response filters. Two infinite-impulse-response (IIR) NPML detection methods are described. The first one uses an embedding technique to achieve IIR noise prediction in combination with a detector trellis that represents a channel target of the partial-response form. The second one employs a detector trellis that corresponds to a generalized partial-response target, such as the one used for traditional NPML based on finite-impulse-response (FIR) prediction filters, and involves a state-reduction technique to deal with the IIR nature of the overall channel. For both methods, data-dependent (DD) variants of the detection algorithm are developed. Implementation aspects are considered to obtain IIR DD-NPML detectors that are dynamically adaptive on user data. Simulation results are given to illustrate the performance of the different detectors with readback signals captured from an actual tape system at various linear recording densities.

Since the inception of direct access magnetic storage about 55 years ago, data storage has both benefited from and given rise to extraordinary progress in many technological areas, including materials science, tribology, servo control and actuation, and signal processing and coding. The number of data bits that can be stored in a unit area - the areal recording density - has increased by eight orders of magnitude for harddisk magnetic storage, with compound annual growth rates at times exceeding 100%. Moreover, the cost of this form of storage has dropped by about seven orders of magnitude. For this reason, data storage has been one of the main enablers of the information technology revolution. According to a recent estimation by the technology analysis firm IDC, the amount of data created worldwide has now started to exceed the capacity of storage that is physically available. This so-called digital universe is forecasted to grow explosively and reach more than 1021bytes (1 ZB) in 2011.

This paper studies loop-delay compensation as a means to improve the robustness of timing recovery loops in tape storage systems. The delay compensation scheme is derived under fairly general assumptions and is found to match a known Kalman-filtering-based solution if a random-walk model of frequency-offset evolution is assumed. Extensions of the scheme to achieve delay compensation in multichannel tape-drive systems that employ global timing control are presented. The practical effectiveness of delay compensation is demonstrated using actual readback waveforms captured on commercial tape drives.

A new approach is introduced for symbol synchronization in multi-channel data storage systems called global timing control (GTC). Applying results from optimum filtering theory to the state-space model of the timing process in multichannel data storage systems, a multi-input multi-output PLL solution is derived. Efficient implementations are developed through simplifications of the optimal solution obtained. The performance of the GTC technique is analyzed using actual read- back waveforms captured in commercial tape drive systems. The results demonstrate the impressive robustness of GTC and its excellent resilience against loss-of-lock phenomena.

This paper describes a fully digital approach for pulse-asymmetry estimation and cancellation in magnetic tape storage systems that employ magneto-resistive (MR) read heads. Algorithms are presented for decision-aided and non-decision- aided estimation of pulse asymmetry. The cancellation of asymmetry is based on a quadratic model of the MR head non- linearity. Using read-back waveforms obtained from commercial tape drives, it is shown that a significant improvement in read-channel performance is achieved by the techniques described. Asymmetry estimation and cancellation using a specific pattern defined in the linear tape open (LTO) tape format are also addressed.

Rate-compatible low-density parity-check (LDPC) codes obtained from the class of array LDPC codes are presented. The design methodology described herein retains practical advantages of array LDPC codes such as excellent performance and efficient encodability across all the codes in a rate-compatible family. Different codes in the rate-compatible family can be specified by a small number of parameters and constructed algebraically with a small amount of preprocessing. The rate-compatible codes can be decoded using a generic decoder architecture, leading to efficient implementations. These properties make the codes attractive for use in DSL systems that need to support a large number of code parameters to cope with channel variability.

We investigate the performance of minimum mean-square error turbo-equalization for LDPC-coded transmission over intersymbol-interference channels. The EXIT-chart technique is used to study the effect of code rate on the convergence of the turbo-equalization process. The analysis is conducted for partial-response channels of various types and for the magnetic recording channel. Performance results obtained from simulations show good agreement with the EXIT-chart analysis. They indicate that for applications requiring high code rates equalizer-based detection may suffer from a nonnegligible loss in performance as compared with maximum a posteriori detection.

Rate-compatible low-density parity-check (LDPC) codes obtained from the class of array LDPC codes are presented. Our approach builds on the deterministic array LDPC code construction and allows efficient encodability across all codes in a rate-compatible family. Furthermore, the use of permutation matrices as building blocks of the parity-check matrix permits efficient decoder implementation. The suitability of rate-compatible array (RCA) LDPC codes for various applications is examined.

We describe a decoder architecture intended for decoding array-code-based low-density parity-check (LDPC) codes using the sum-product algorithm (SPA). The advantages of the proposed architecture, as compared to the fully parallel implementation of the SPA, are: reduced memory size, avoidance of complex signal interconnect patterns, and ease of programmability to accommodate various code parameters. These advantages are derived from exploiting the well-defined structure of the parity-check matrix of array-code based LDPC codes. Sum-product decoding with modified message-passing schedules are proposed to simplify the decoder implementation further.

The paper investigates the application of low-density parity-check (LDPC) codes to digital subscriber-line (DSL) transmission systems that employ discrete multitone modulation. A family of linear-time encodable binary LDPC codes that are well-suited for DSL transmission is introduced. Encoding and symbol mapping for multilevel modulation are described. Simulation results show that even under tight latency constraints good net coding gains can be achieved. Implementation complexity is analyzed and compared with that of trellis-coded modulation as employed in current asymmetric DSL transceivers. The incorporation of powerful LDPC coding techniques into next-generation DSL modems appears to be possible with reasonable increase in transceiver complexity.

A filter-bank modulation technique called filtered multitone (FMT) and its application to data transmission for very high-speed digital subscriber line technology are described. The proposed scheme leads to significantly lower spectral overlapping between adjacent subchannels than for known multicarrier techniques such as discrete multitone (DMT) or discrete wavelet multitone. FMT modulation mitigates interference due to echo and near-end crosstalk signals, and increases the system throughput and reach. Signal equalization in an FMT receiver is accomplished in the form of per-subchannel symbol-spaced or fractionally spaced linear or decision-feedback equalization. The problem of channel coding for this type of modulation is also addressed, and an approach that allows combined removal of intersymbol-interference via precoding and trellis coding is described. Furthermore, practical design aspects regarding filter-bank realization, initial transceiver training, adaptive equalization, and timing recovery are discussed. Finally, simulation results of the performance achieved by FMT modulation for very high-speed digital subscriber line systems, where upstream and downstream signals are separated by frequency-division duplexing, are presented and compared with DMT modulation.

Digital subscriber line (DSL) technology for high-speed data transmission over the local-loop telephone twisted pairs was advanced in the labs of several research institutions during the late 1980’s and early 1990’s. Researchers began to develop and experiment with new transmission ideas and to realize high-speed modems in prototype form. As technology matured and standards evolved, these modems came to be known collectively as “xDSL” modems. The ISDN basic-rate interface, which was developed during the early 1980’s and operated at a “mere” 160 kb/s, today is often cited as being the archetype of this technology.

100BASE-T2 is a new physical layer specification for IEEE 802.3 LANs operating at 100 Mbit/s ("fast Ethernet"). It enables users of the 10BASE-T Ethernet LAN technology to upgrade their networks from 10 Mbit/s to 100 Mbit/s performance while retaining an existing voice-grade cabling infrastructure. 100BASE-T2 transceivers will operate over two pairs in unshielded twisted-pair cables corresponding to EIA/TIA category 3 (UTP-3), which is the minimum requirement for 10BASE-T. In a four-pair UTP-3 cable, simultaneous operation of two 100BASE-T2 links, or one 100BASE-T2 and one 10BASE-T link, is permitted. Since voice-grade cables exhibit more signal attenuation and significantly higher crosstalk coupling between adjacent pairs than data-grade cables, sophisticated digital signal processing techniques are needed to achieve reliable 100 Mbit/s transmission. The 100BASE-T2 standard defines dual-duplex baseband transmission at a modulation rate of 25 MBaud. During each modulation interval, a four-bit data nibble or Ethernet specific control information is encoded into a pair of quinary signals. These signals are transmitted simultaneously on the two wire pairs in both signalling directions. In the receivers, adaptive digital filters are required for echo and NEXT cancellation, equalization, and interference suppression.

This paper deals with multilevel partial-response class-IV (PRIV) transmission over unshielded twisted-pair (UTP) cables. Specifically, transmission at a rate of 155.52 Mb/s over data-grade UTP cables for local-area networking is considered. As a low-complexity method used to compensate for cable-length dependent signal distortion, adaptive analog equalization with two controlled parameters is proposed: one parameter determines a frequency-independent receiver gain, the other parameter controls the transfer characteristic of a variable analog receive-filter section. For the stepwise design of the transmit and receive filters, a combination of analytic techniques and simulated annealing is employed. First, the variable equalizer section, then the remaining fixed analog receive filter section are developed and finally the analog transmit filter is determined. The paper also describes the adjustment of the equalizer section, and the control of the sampling phase in the receiver front-end. The two equalizer parameters are controlled by an algorithm that operates on the sampled signals and adjusts these parameters to optimum settings independently of the sampling phase. The latter is controlled by a decision-directed phase-locked loop algorithm that becomes effective when equalization has been achieved. The dynamic behaviour and mean-square error in steady-state obtained with these control algorithms are investigated.

The paper describes an experimental transceiver for full-duplex transmission at a rate of 125 Mbit/s over unshielded twisted-pair cables of ordinary voice-grade quality, intended for use in a fiber distributed data interface (FDDI) network. Quaternary partial-response class-IV (QPRIV) overall-channel signaling with near-end crosstalk (NEXT) cancellation and maximum-likelihood sequence detection is employed. The spectral shape of the QPRIV signals facilitates equalization and achieving compliance with EMC regulations. Since in an FDDI system each transmitter can be clocked independently, the receiver must cope with phase drift between NEXT signals to be cancelled and signals received from the remote transmitter. With the chosen transceiver architecture, digital-to-analog conversion of transmit signals, analog-to-digital conversion of receive signals, and adaptive NEXT cancellation are performed synchronously with the transmitter clock. The rate change from transmit timing to controlled receive timing is accomplished by an adaptive equalizer in conjunction with an elastic buffer and occasional coefficient shifts. The equalizer is adjusted rapidly enough to allow for a maximal phase drift of ±100 ppm. The implementation of all digital signal-processing functions in a single 0.5 μm CMOS VLSI prototype chip is discussed. The employed standard-cell design resulted in a power consumption of 6 W. Significantly lower power consumption can be achieved by custom design of highly repetitive processing elements

The problem of preventing quasi-catastrophic error propagation in maximum-likelihood and reduced-state sequence detection for multilevel partial-response channels with transfer functions (1-D/sup P/) and (1+D/sup P/) is studied. M-ary channel input sequences that limit the length of minimum distance error events to L symbols are exhaustively characterized by finite-state transition diagrams. An efficient procedure for computing the capacity associated with these transition diagrams is given. Efficient constrained codes that can be readily implemented by finite-state encoders and block decoders with small error propagation are constructed.>

The paper describes the decoding of unconstrained L-ary signals (L/spl ges/2) transmitted over a noisy partial-response channel with transfer function 1-D/sup 2/. Signals received at even and odd sampling times are independently decoded in a pipeline fashion. After stating the known results for full-state maximum-likelihood sequence decoding, a 2-state decoding algorithm is introduced in which the difference between the metrics of the retained two most-likely states is iteratively computed. An analysis of its error-event probability shows that two types of error events are most likely, regular free-distance events and induced free-distance events. The latter cause only a rather small degradation of error performance compared to full-state decoding. In addition, the symbol-error probability for modulo-L encoded user symbols and decoding with finite decoding delay is computed. The 2-state decoder can be realized for arbitrary values of L with low hardware complexity.>

This work is concerned with the problem of designing reduced-complexity Viterbi decoders for the transmission of digital data over intersymbol interference channels. First, optimal state-grouping for constructing reduced-state trellises is presented and illustrative examples are given for multilevel transmission over partial-response channels of the type 1+or-D/sup n/, (1+D)/sup 2/, (1+D)/sup 2/(1-D), and (1+D)/sup 3/(1-D). Then, the quaternary 1-D type partial-response channel is considered in more detail and a difference-matric algorithm employing state-reduction is derived and shown to result in a simple decoding scheme.>

Partial response class-IV signaling combined with Viterbi decoding to perform maximum-likelihood sequence detection is considered for high-speed data transmission over twisted-pair cables. In order to establish which data rates and distances can be achieved by this method, a performance evaluation is conducted. Binary and quaternary modulations are considered, and disturbance of the received signal by near-end and far-end crosstalk and additive white Gaussian noise is taken into account. A benchmark comparison with rigorously optimized symbol-by-symbol detection systems using AMI and HDB3 line coding is presented.>