Reliability in cloud AI infrastructure is crucial for cloud service providers, prompting the widespread use of hardware redundancies. However, these redundancies can inadvertently lead to hidden degradation, known as “gray failure”, for AI workloads, significantly affecting end-to-end performance and concealing performance issues, which complicates root cause analysis for failures and regressions. We introduce SuperBench, a proactive validation system for AI infrastructure that mitigates hidden degradation caused by hardware redundancies and enhances overall reliability. SuperBench features a comprehensive benchmark suite, capable of evaluating individual hardware components and representing most real AI workloads. It comprises a Validator that learns benchmark criteria to pinpoint defective components clearly. Additionally, SuperBench incorporates a Selector to balance validation time and issue-related penalties, enabling optimal timing for validation execution with a tailored subset of benchmarks. Through testbed evaluation and simulation, we demonstrate that SuperBench can increase the mean time between incidents by up to 22.61×. SuperBench has been successfully deployed in Azure production, validating hundreds of thousands of GPUs every year.

We present a novel storage manager for multi-dimensional arrays that arise in scientific applications, which is part of a larger scientific data management system called TileDB. In contrast to existing solutions, TileDB is optimized for both dense and sparse arrays. Its key idea is to organize array elements into ordered collections called fragments. Each fragment is dense or sparse, and groups contiguous array elements into data tiles of fixed capacity. The organization into fragments turns random writes into sequential writes, and, coupled with a novel read algorithm, leads to very efficient reads. TileDB enables parallelization via multi-threading and multi-processing, offering thread-/process-safety and atomicity via lightweight locking. We show that TileDB delivers comparable performance to the HDF5 dense array storage manager, while providing much faster random writes. We also show that TileDB offers substantially faster reads and writes than the SciDB array database system with both dense and sparse arrays. Finally, we demonstrate that TileDB is considerably faster than adaptations of the Vertica relational column-store for dense array storage management, and at least as fast for the case of sparse arrays.

Exploring the vast microarchitectural design space of chip multiprocessors (CMPs) through the traditional approach of exhaustive simulations is impractical due to the long simulation times and its super-linear increase with core scaling. Kernel based statistical machine learning algorithms can potentially help predict multiple performance metrics with non-linear dependence on the CMP design parameters. In this paper, we describe and evaluate a machine learning framework that uses Kernel Canonical Correlation Analysis (KCCA) to predict the power dissipation and performance of CMPs. Specifically we focus on modeling the microarchitecture of a highly multithreaded CMP targeted towards packet processing. We use a cycle accurate CMP simulator to generate training samples required to build the model. Despite sampling only 0.016% of the design space we observe a median error of 6-10% in the KCCA predicted processor power dissipation and performance.

Traditional FPGA education either involves a physical laboratory room with workstations connected to individual FPGA experimenter boards or simulation platforms. Physical labs are expensive to maintain and require substantial floor space. In addition, students need to be physically present in the laboratories to access the FPGA boards. On the other hand, it is often the case that simulation platforms do not provide the students an adequate, in-depth understanding of concepts (such as synthesis on FPGAs). In this short paper, a third option - a remote FPGA Laboratory - is illustrated. This option uses software to allow students and researchers in geographically distributed locations to remotely access a pool of 64 Xilinx ML-310 Boards over the Internet. To the best of our knowledge, a remote FPGA facility of this kind is unique. The infrastructure described here gives remote users the ability to dynamically power on/off the FPGA boards, upload/download files, configure the boards online and execute synthesized designs while sending input and output through the Internet. Advantages include considerable savings in space, greater accessibility for users, ease of maintenance, and the ability to better schedule resources.

We present an automated design flow for minimizing the use of diodes and switches (active devices) in design implementations on a nanofabric based on chemically self-assembled electronic nanotechnology as proposed in Goldstein and Budiu [2001]. Connectivity and logic in the nanofabric are realized using the switch and diode behaviors of molecular devices, unlike very large scale integrated (VLSI) circuits where complementary metal-oxide semiconductor (CMOS) gates are used. Similar to the optimization goal of reducing the number of gates in VLSI designs to minimize area, power dissipation, and delay, decreasing the number of switches and diodes used in the nanofabric can potentially minimize design implementation area and power dissipation, besides reducing the delay and signal drop between latched stages in order to improve performance. An integrated placement, topology selection, and routing approach for design implementation on the nanofabric is proposed. Note that this problem is fundamentally different from CMOS VLSI placement and routing because of the inherent routing-dependent logic realization in our target nanofabric. To the best of our knowledge this is the first reported work on automated integrated placement, topology selection, and routing for diode-based nanofabrics. A practical and scalable simulated annealing-based placement and routing algorithm has been implemented. On average, the integrated placement and routing approach achieves a reduction of 12% in the number of switches and diodes used for MCNC benchmarks, compared to separate placement and routing optimization results. The maximum reduction achieved in the number of active devices using our approach is 24%, and in general, we observed that the bigger the benchmark, the larger the improvement achieved.