Physical Design (PD) issues are becoming a major challenge with technology scaling in integrated circuits. Multi-aggressor crosstalk, power supply noise and ground bounce are some of the PD issues that cause considerable path delay variations. Therefore, these PD issues need to be considered during path delay testing to ensure better delay defect coverage. In this paper, we first show that the path delay Automatic Test Pattern Generation (ATPG) test methods are incapable of generating an input pattern that can capture worst-case path delay in circuits. We, then present our Physical Design Aware Pattern Generation (PDAPG) method to generate an input test pattern that can capture worst-case path delay in the presence of PD issues. We propose a backtrace X-filling approach to identify the relevant X-bits causing worst-case path delay. Simulations performed on ITC'99 benchmark circuits show that our PDAPG method is capable of providing high quality input test patterns in comparison with conventional path delay ATPG test methods.

In current technologies, the robustness of Static Random Access Memories (SRAM) has to be investigated under any possible source of disturbance. In this paper, we evaluate the reliability of an SRAM cell exposed to atmospheric neutron radiation, affected by random threshold voltage variation and under different operation conditions (supply voltage, process corner and temperature). The SRAM cell's Soft Error Rate (SER) at simulation level is estimated using accurate models of atmospheric neutron induced currents. The study shows that in extreme operation conditions and under random process variability, the SER of an SRAM can reach values up to 3X larger than the nominal value, or down to 2X smaller than the nominal value. This large SER range confirms the importance of our study and justifies the need for further evaluation of circuits under radiation at the simulation level.

Memory design and test represent very important issues. Memories are designed to exploit the technology limits to reach the highest storage density and high-speed access. The main consequence is that memory devices are statistically more likely to be affected by manufacturing defects. The challenge of testing SRAM memories consists in providing realistic fault models and test solutions with minimal application time. Due to the complexity of the memory device, fault modeling is not trivial. Classical memory test solutions cover the so-called `static faults' (such as stuck-at, transition, and coupling faults) but are not sufficient to cover faults that have emerged in latest VDSM technologies and which are referred to as `dynamic faults'. This tutorial aims at introduce and guide to new test approaches developed so far for dealing with dynamic faults in the latest generation of SRAM memories.

In this paper, a novel hybrid fault tolerant architecture for digital circuits is proposed in order to enable the use of future CMOS technology nodes. This architecture targets robustness, power consumption and yield at the same time, at area costs comparable to standard fault tolerance schemes. The architecture increases circuit robustness by tolerating both transient and permanent online faults. It consumes less power than the classical Triple Modular Redundancy (TMR) approach while utilizing comparable silicon area. It overcomes many permanent faults occurring throughout manufacturing while still tolerating soft errors introduced by particle strikes. These can be done by using scalable redundancy resources, while keeping the hardened combinational logic circuits intact. The technique combines different types of redundancy: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error tolerance. Results on largest ISCAS and ITC benchmark circuits show that our approach has an area cost negligible of about 2% to 3% with a power consumption saving of about 30% compared to TMR. Finally, it deals with aging phenomenon and thus, increases the expected lifetime of logic circuits.

Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors.

The Flash technology is the most popular non-volatile memory technology. In this paper, we present the ability of a SPICE-like model of the ATMEL TSTAC™ eFlash technology to guide the design and test phases. This model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. It is able to guide the test phase since it allows analyzing and modeling defects that may affect the eFlash array. This analysis highlights the interest of the proposed model to identify a realistic set of fault models that has to be tested, thus enhancing existing solutions for TSTAC™ eFlash testing. The proposed model is also helpful to guide the design phase. Data presented in the paper demonstrate its accuracy compared to silicon measurements, usefulness to predict the technology shrinking and usefulness to guide the pulse programming method.

As technology scales down, the effects of power supply noise and ground bounce are becoming significantly important. In the existing literature, it has been shown that excessive power supply noise can affect the path delay, while ground bounce is either neglected or assumed similar to power supply noise. In this work, we present a detailed study of combined and uncorrelated power supply noise and ground bounce and their impact on the path delay. Our analyses show that different combination of power supply noise and ground bounce can lead to either delay speed-up or slow-down. Furthermore, our study shows the degrading influence of supply noise resonance on the path delay. We perform HSPICE simulations for path delay analysis on various technology nodes i.e. 130nm, 90nm, 65nm and 45nm.

A comprehensive SRAM test must guarantee the correct functioning of each cell of the memory (ability to store and to maintain data), and the corresponding addressing, write and read operations. SRAM testing is mainly based on the concept of fault model used to mimic faulty behaviors. Traditionally, the effects of bit line coupling capacitances have not been considered during the fault analysis. However, recent works show the increasing impact of bit line coupling capacitances on the SRAM behavior. This paper reviews and discusses preview works addressing the issues coming from bit line parasitic capacitances and data contents on SRAM testing, pointing out the impacts of these effects on the existing test solutions. Then, we introduce two optimizations of the state-of-the-art test solution able to take into account the influence of bit line coupling capacitances while reducing the test length of about 60% and 80%, respectively.

High power consumption during test may lead to yield loss and premature aging. In particular, excessive peak power during at-speed delay fault testing represents an important issue. In the literature, several techniques have been proposed to reduce peak power consumption during at-speed LOC or LOS delay testing. On the other hand, some experiments have proved that too much test power reduction might lead to test escape and reliability problems. So, in order to avoid any yield loss and test escape due to power issues during test, test power has to map the power consumed during functional mode. In literature, some techniques have been proposed to apply test vectors that mimic functional operation from the switching activity point of view. The process consists of shifting-in a test vector (at low speed) and then applying several successive at-speed clock cycles before capturing the test response. In this paper, we propose a novel flow to determine the functional power to be used as test power (upper and lower) limits during at-speed delay testing. This flow is also used for comparison purpose between the above-mentioned test scheme and power consumption during the functional operation mode of a given circuit. The proposed methodology has been validated on an Intel MC8051 micro controller synthesized in a 65 nm industrial technology.

This paper proposes an innovative approach to cope with defects in SRAM bit-cell array. Traditional approaches use spare parts (rows, columns or blocks) to replace defective bit-cells. Instead of replacing defective bit-cells, we propose to operate the SRAM with reduced storage capacity whenever defective bit-cells are present. We implement this feature through a programmable combinational logic, called Scrambling Module (SM), which scrambles the memory addresses. The scrambling changes the addresses of the defective bit-cells, grouping them in an idle address zone located at the end of the memory address plan. The SM is described by using a mathematical formulation based on linear algebra. The proposed technique can be used in combination with traditional redundancy approaches using spare rows and/or columns. The effectiveness of three different SM is demonstrated, considering a 1MBit SRAM. For a given level of defect tolerance, it is shown that our technique can reduce the amount of spare area by several orders of magnitude. Moreover, as the SM is implemented as an external block, it does not affect the maximum operation frequency of the SRAM. Instead, it affects the memory access delay.

This paper addresses the problem of logic diagnosis of System-on-Chip (SoC). We propose a diagnosis approach based on a matching algorithm between a set of predicted failures and the set of failures observed during the test phase. The result of the diagnosis is a ranked list of suspected nets able to explain the observed failures. Experimental results show the diagnosis accuracy of the proposed approach in terms of absolute number of suspects. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.

This paper introduces a simulator that allows analyzing the radiation induced errors on memory devices. The simulator takes all the radiation effects on SRAM into account and can be easily tuned on the base of data gained during radiation experiments and/or presented in literature. We also present a case study application in which the proposed simulator is used to validate a low-cost hardware platform for soft error detection in avionic environment by the mean of atmospheric balloons in the context of HAMLET project.

Reliability analysis of SRAM core-cells requires statistical methods with very high accuracy to cope with very low failure probabilities. Although new statistical methods have been recently proposed, to the best of our knowledge, there is no method able to evaluate the joint failure probability (the probability that at least one failure mechanism occurs) of an SRAM core-cell with enough accuracy in a reasonable time. We propose a statistical simulation method based on the analytical integration of the multivariate Gaussian distribution function.

At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this paper, we propose a comparison between the two testing schemes in terms of transition fault coverage and power consumption, in order to quantify the pros and cons of LOS with respect to LOC. This study shows that LOS not only exhibits higher performance in coverage but also does not require as much extra power as predicted, especially in terms of peak power. These facts may represent convincing arguments for its wider use and development.

In this paper, we present a comparative study on the effects of resistive-bridging defects in the SRAM core-cells, considering different technology nodes. In particular, we analyze industrial designs of SRAM core-cell at the following technology nodes: 90nm, 65nm and 40nm. We have performed an extensive number of simulations, varying the resistive value of defects, the power supply voltage, the memory size and the temperature. Experimental results show malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array.

In the context of SRAM testing, we propose a methodology to define proper conditions under which SRAMs should be tested to improve their reliability. This methodology is especially suitable to deal with the impact of threshold voltage variability affecting SRAM core-cell transistors. By establishing an objective manner of comparing different test conditions, the proposed study shows how it is possible to detect SRAM core-cells with poor quality by applying a reduced set of test runs. The proposed methodology also allows determining the most appropriate DfT (Design-for-Test) technique for each peculiar SRAM design and technology.

Flash memories are based on the floating gate technology allowing the write and erase data electronically. Such a technology can be prone to complex defects leading to faulty behaviors. In this paper, we introduce an electrical model of the ATMEL TSTACTM eFlash memory technology. The model is composed of two layers: a functional layer representing the floating gate and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model has been validated by means of simulations and comparisons with ATMEL silicon data. We apply this model for the analysis of defect-induced failures. As a case study, a resistive defect injection is considered.

In this paper we investigate the possibility of using commercial synthesis tools to build parity predictors for nano-electronic gates designs. They will be used as redundant resources for robustness improvement for future CMOS technology nodes.

This study investigates the reasons why test power reduction through X-filling techniques works well for cycle-average power reduction but is not so efficient concerning instantaneous peak power reduction.

Negative Bias Temperature Instability (NBTI) is a degradation phenomenon that occurs in PMOS transistors during circuit lifetime. Recent works have proposed transistor level and circuit level models that allow designers to deal with such phenomenon. Based on these models and taking into account Random Dopant Fluctuation (RDF), we study the possibility of detecting SRAM core-cells that are prone to NBTI failures during post-production test. For this purpose, we introduce a statistical simulation method that allows estimating the amount of NBTI affected core-cells that pass or fail under given test conditions. Supply voltage, temperature, word line pulse width, word line pulse voltage and bit line voltage are the parameters considered as test conditions. An industrial core-cell design with a 65 nm technology is used as case study.

This paper presents a comprehensive framework for logic diagnosis consisting of two main phases. In the first phase, a set of suspected faulty sites is obtained by applying an approach based on an Effect-Cause analysis. Then, in the second phase, a set of realistic fault models is associated with each suspected faulty site by analyzing specific information, called fault evidences, collected during the first phase. The main advantage of the proposed methodology is its capability to deal with several fault models at the same time. Another advantage is that it is able to handle both single and multiple fault occurrences. Experiments on ISCAS85, ISCAS89, and ITC99 benchmark circuits show the efficiency of the proposed method both in terms of diagnosis resolution and accuracy of the predicted fault models.

The importance of delay faults proportionally increases when entering in the nano-technology era, and logic diagnosis must localize delay faults as precisely as possible to speed-up yield ramp-up. This paper presents a logic diagnosis approach targeting delay faults. The proposed approach is based on the single-location-at-a-time (SLAT) paradigm used to determine a set of suspects. It addresses the case of sequential circuits tested at-speed. The main advantages of this approach are that it can manage a comprehensive set of delay faults, and that it is independent on the size of the delay (induced by the fault). Experimental results show the effectiveness of the proposed approach in terms of absolute number of suspects.

Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern in VDSM technologies. It provides information about the SRAM design reliability, and its effectiveness is therefore mandatory for safety applications. Existing core-cell stability design-for-test (DfT) techniques consist in controlling the voltage levels of bit lines to apply a weak write stress on the core-cell under test. If the core-cell is weak, the weak write stress induces the faulty swap of the core-cell. However, these solutions are costly in terms of area and test application time, and generally require modifications of critical parts of the SRAM (core-cell array and/or the structure generating the internal auto-timing). In this paper, we present a new DfT technique for stability fault detection. It consists in modulating the word line activation in order to perform an adjustable weak write stress on the targeted core-cell for stability fault detection. Compared to existing DfT solutions, the proposed technique offers many advantages: programmability, low area overhead, low test application time. Moreover, it does not require any modification of critical parts of the SRAM.

This paper presents a logic diagnosis approach targeting bridging faults. The proposed approach is performed in two phases, (i) a fault localization phase based on the single-location-at-a-time (SLAT) paradigm determining a set of suspects, and (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal at the same time with several bridging fault models leading to either static or dynamic faulty behaviors. Experimental results on full scan circuits show the diagnosis accuracy of the proposed approach in terms of absolute number of suspects. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.

This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault simulation. The main advantages of the proposed approach are that it is highly computationally efficient with respect to state-of-the-art fault simulation techniques, and that it encompasses different delay sizes in one simulation pass without resorting to an improved transition fault model. Preliminary results on ITC99 benchmarks show that the gain in terms of CPU time is up to one order of magnitude compared to previous existing techniques.

Embedded flash memories are dominated by the NOR architecture but NAND is becoming more and more adopted due to its high storage capacity. This paper presents a preliminary study on actual defects in NAND array.

In this paper, we present an exhaustive analysis of resistive- open defects in sense amplifiers of static random access memory designed with a 65 nm technology. We show that some resistive-open defects may lead to a new type of dynamic behavior that has never been experienced in the past. It is modeled by dynamic two-cell incorrect read faults of two different types. Such fault models represent failures in the sense amplifier, which prevent it from performing any read operations (in case of type 1 [1]) or only a single type of read operation (in case of type 2). Results of electrical simulations are presented to provide a complete understanding of such a faulty behavior and possible March test solutions are proposed to detect all d2cIRFs.

Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, and its effectiveness allows a fast yield ramp up. Most of existing diagnosis methods uses a fault dictionary to provide detailed information of fault localization. However, these solutions are most of the time unable to distinguish between all faults, and more importantly often fail to identify the actual faulty block of the memory. Identifying which block of a memory (core- cell array, write drivers, address decoders, pre-charge circuits, etc ...) is defective allows saving considerable amount of time during the ramp up phase. In this paper, we propose a very low cost design-for-diagnosis (DfD) solution for identifying faulty write drivers. It consists in verifying logic and analog conditions that guarantee the fault-free behavior of the write driver. The proposed solution allows a fast diagnosis (only three consecutive write operations are needed to fully diagnose the write driver) and induces a low area overhead (about 0.5% for a 512 times 512 SRAM). Beside diagnosis, an additional interest of such a solution is its usefulness during a post-silicon characterization process, where it can be used to extract the main features of write drivers (logic and analog levels on bit lines).

With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical triple modular redundancy (TMR) architecture interesting for a yield improvement purpose.

The usual techniques for memory diagnosis are mainly based on signature analysis. They consist in creating a fault dictionary that is used to determine the correspondence between the signature and the fault models affecting the memory. The effectiveness of such diagnosis methods is therefore strictly related to the fault dictionary accuracy. To the best of our knowledge, most of existing signature-based diagnosis approaches targets static faults only. In this paper, we present a new diagnosis approach that represents an alternative to signature-based approaches. This new diagnosis technique, named history-based diagnosis, makes use of the effect-cause paradigm already developed for logic design diagnosis. It consists in creating a database containing the history of operations (read and write) performed on a faulty memory core-cell. This information is crucial to track the root cause of the observed faulty behavior and it can be used to generate the set of possible fault primitives representing the set of suspected fault models. This new diagnosis method is able to identify static as well as dynamic faults. Although applied to SRAMs in this paper, it can be effective also for other memory types such as DRAMs. Experimental results are provided to prove the efficiency of the proposed methodology in generating a list of suspected faults as well as the location of the faulty components in the memory.

Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR architectures for logic cores to increase SoC yield.

Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, and its effectiveness allows a fast yield ramp up. Most of existing diagnosis methods uses a fault dictionary to provide detailed information on fault localization. However, these solutions are most of the time unable to distinguish between all faults, and more importantly often fail to identify the actual faulty block of the memory. Identifying which block of a memory (core- cell array, write drivers, address decoders, pre-charge circuits, etc ...) is defective allows to saving considerable amount of time during the ramp up phase. In this paper, we propose a very low cost design-for- diagnosis (DfD) solution for identifying faulty write drivers. It consists in verifying logic and analog conditions that guarantee the fault-free behavior of the write driver. The proposed solution allows a fast diagnosis (only three consecutive write operations are needed to fully diagnose the write driver) and induces a low area overhead (about 0.5% for a 512 times 512 SRAM). Beside diagnosis, an additional interest of such a solution is its usefulness during a post-silicon characterization process, where it can be used to extract the main features of the write drivers (logic and analog levels on bit lines).

Nanoscaled SRAMs are now becoming more and more prone to device parameter deviations. In this paper, we consider threshold voltage (Vt) deviations in 6T core-cells designed with 90 nm technology. Static faults (transition and read destructive) but also dynamic faults (dynamic read destructive) are obtained as resulting faulty behaviors. Moreover, electrical data show that PVT (process, voltage, temperature) corners that maximize the detection of these faults are quite unconventional. Especially, we show that Vt deviations have their main impact at low voltage while hard defects, such as resistive-open defects in the core-cell, better manifest themselves at high voltage. This study of parameter deviations opens an additional problematic for the test of nanoscaled SRAMS that will be much more severe in deeper technologies (65 nm and 45 nm).

In this paper, we present a diagnosis methodology targeting the whole set of bridging faults leading to either static or dynamic faulty behavior. The adopted diagnosis algorithm resorts only to logic information provided by the tester without requiring a detailed description of the fault models. It is based on an Effect-Cause analysis providing a ranked list of suspects always including the root cause of the observed error. Experimental results on benchmarks ISCAS'89 and ITC '99 show the efficiency of the proposed solution in terms of diagnosis resolution and required computational time.

This paper presents an analysis of the electrical origins of slow write driver faults (SWDFs) (van de Goor et al., 2004) that may affect SRAM write drivers in 65nm technology. This type of fault is the consequence of resistive-open defects in the control part of the write driver. It involves an erroneous write operation when the same write driver performs two successive write operations with opposite data values. In the first part of the paper, we present the SWDF electrical phenomena and their consequences on the SRAM functioning. Next, we show how SWDFs can be sensitized and observed and how a standard March test is able to detect this type of fault

The embedded flash technology can be subject to complex defects creating functional faults. In this paper, we describe the different steps in the electrical modeling of 2T-FLOTOX core-cells for a good understanding of failure mechanisms. First, we present a first order electrical model of 2T-FLOTOX core-cells which is characterized and compared with silicon data measurements based on the ATMEL 0.15 mum eFlash technology. Next, we propose a study of resistive defect injections in eFlash memories to show the relevance of the proposed simulation model. At the end of the paper, a table summarizes the functional fault models for different resistive defect configurations and experimental set-ups. According to these first results and with additional analysis of actual defects presented in [1] we are then able to enhance existing test solutions for eFlash testing.

In this paper, we present an analysis of resistive-open defects in the sense amplifier of SRAMs designed with the Infineon 65 nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been published in the past. This faulty behavior can be modeled as a dynamic two-cell Incorrect Read Fault (d2cIRF). Such d2cIRF is the consequence of a failure in the sense amplifier which prevents it to perform any read operations. We show that it requires a specific sequence of read operations to be detected. Results of electrical simulations are presented to give a complete understanding of such a faulty behavior. Finally, a possible March test solution is presented to allow the detection of d2cIRFs in all sense amplifiers of an SRAM.

This paper presents DERRIC (Diagnosis of logic ERRors in VLSI Integrated Circuits), a diagnostic tool targeting most of the fault models used in practice today. This tool is intended to be used to diagnose faulty behaviors in nanometric circuits for which the classical stuck-at fault model is far to cover all the realistic failures. The underlying method of DERRIC is based on the Effect-Cause approach which relies on the two following main operations. The first one is based on critical path tracing (CPT) that consists in identifying critical lines in the Circuit Under Test (CUT) which can be the source of observed errors. The second one consists in allocating a set of possible fault models to each critical line, so that root causes of failures can be finally determined. The main advantage of this method is that it does not need to explicitly consider each fault model during the diagnosis process. Experiments on ISCAS'85 and ITC'99 benchmarks show the efficiency of the proposed tool in terms of diagnosis resolution.

The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like Flash. As any kind of memories, embedded Flash (eFlash) can be subjected to complex functional faults that are related to their particular technological process and to their integration density. In this paper, we address a major issue during eFlash testing, namely the test of Address decoder Faults (AFs), which is generally very time consuming with ad-hoc solutions presently used in industry. In the first part of the paper, we show the impact of AFs on the functional behavior of an eFlash. Next, we use an analogy with RAM memory testing to classify AFs with respect to their functional behavior. We then obtain AFs acting either as stuck-at faults or as state coupling faults. In the fourth part of the paper, we propose a concurrent approach for testing AFs acting on either the word line decoder or the bit line decoder. The proposed approach allows using a minimal number of programming operations during test application. Finally, we propose a compaction procedure to further reduce the test time of AFs. As a result, huge reductions in test time can be achieved; experiments on a 4 Mbits eFlash have shown that a test time reduction factor of 34x can be obtained when compared to the global eFlash test flow presently used in industry. An additional important feature of the proposed strategy is that it allows testing 100% of other critical faults in eFlashs (stuck-at, transition and state coupling faults) beside full coverage of AFs.

The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like flash. Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, the authors analyze the impact of a defective tunnel window oxide thickness. The authors show that this defective oxide thickness impacts erase or/and write operations as well as the retention and reliability of the eFlash. The proposed solution to detect such a defective oxide consists in using the voltage disturbance due to the coupling phenomenon existing between bit lines. This particular defective mechanism can be modeled as a coupling fault, especially a state coupling fault. Based on this analysis, the authors propose a test solution that uses two checkerboard patterns; checkerboard pattern (CKB) and its complement (CKBI). The authors show that these two patterns have to be applied by using a parallel programming approach, which allows to increase the coupling phenomenon and thus the voltage disturbance

In this paper, we present an analysis of resistive-open defects in the write driver of SRAMs designed with the Infineon 65nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been experienced in the past. This faulty behavior can be modeled as an un-restored destructive write fault (URDWF). Such URDWF is a consequence of the structural dependencies that exist between the write driver and the sense amplifier, and appears when a specific read operation is performed immediately after a specific write operation. Results of electrical simulations are presented to give a complete understanding of such a faulty behavior and to highlight the difference with a standard un-restored write fault (URWF) model. Next, a possible March test solution is presented to detect URDWF. Finally, a discussion is proposed on the opportunity to include new features in this part of the memory to easily distinguish between faults coming from the write driver (like URDWF) and those coming from other parts of the memory (sense amplifier, core-cells, etc.)

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, the authors propose in this paper to modify an existing test data compression technique so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded intellectual property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 20times reduction in test data volume and 95% test power reduction can be obtained simultaneously

Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant so as to avoid noise phenomena such as IR-drop or Ground Bounce. Then, we propose a solution based on power-aware assignment of don't care bits in deterministic test patterns that considers structural information of the circuit under test. Experiments have been performed on ISCAS'89 and ITC'99 benchmark circuits with the proposed structural-based power-aware X-filling technique. These results show that the proposed technique provides the best tradeoff between peak power reduction and increase of test sequence length

Non-volatile flash memories are becoming more and more popular for system-on-chip design (SoC). Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. Studies of realistic failure mechanisms and their associated fault models are the first mandatory step before providing efficient and practical new test methods. In this paper, we present an analysis made on actual failures occurring in 2T FLOTOX cells of 0.15mum NOR-based embedded flash structure

Resistive-open defects appear more and more frequently in VDSM technologies. In this paper we present a study concerning resistive-open defects in the core-cell of SRAM memories. The first target of this work is a comparison of the effect produced by resistive-open defects in the 0.13 μm and 90 nm core-cell. We show that the 90 nm core-cell is more robust than the 0.13 μm core-cell in presence of resistive-open defects. On the other hand we show that dynamic faults are most likely to occur in the 90 nm than in 0.13 μm core-cell. Finally we propose a unique March test solution that ensures the complete coverage of all the extracted fault models for both technologies.

In this paper, we present an exhaustive study on the effects of resistive-open defects in the pre-charge circuits of SRAM memories. In particular, we have analyzed the influence of resistive-opens placed in different locations of these circuits. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled with un-restored write faults (URWFs) and un-restored read faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate that the test of URWFs is more rentable in terms of resistive defect detection than that of URRFs.

In this paper, we present a novel study on data retention faults (DRFs) in SRAM memories. We analyze in detail the electrical origins of these faults, starting from the most common till those that lead to what we have called hard to detect DRFs. In general, DRFs are supposed to be produced by very high resistive-open defects that affect the refreshment loop of the core-cell. We demonstrate that lower values of resistance may produce hard to detect DRFs. Moreover, each resistive-open defect produces a particular faulty behavior of the core-cell that changes for different ranges of the resistive value. We analyze different cases and we propose for each one an efficient test procedure based on March tests. In particular, we propose to stimulate the defective cells in some cases by indirect accesses and in some other cases by emphasizing natural noise phenomenon of SRAM memories (such as the ground bounce).

In this paper we present an exhaustive analysis of resistive-open defect in core-cell of SRAM memories. These defects that appear more frequently in VDSM technologies induce a modification of the timing within the memory (delay faults). Among the faults induce by such resistive-open defects there are static and dynamic read destructive fault (RDF), deceptive read destructive fault (DRDF), incorrect read fault (IRF) and transition fault (TF). Each of them requires specific test conditions and different kind of March tests are needed to cover all these faults (TF, RDF, DRDF and IRF). In this paper, we show that a unique March test solution can ensure the complete coverage of all the faults induced by the resistive-open defects in the SRAM core-cells. This solution simplifies considerably the problem of delay fault testing in this part of SRAM memories.

Scan-based architectures, though widely used in modern designs, are expensive in power consumption. Recently, we proposed a technique based on clustering and reordering of scan cells that allows to design low power scan chains according to Y. Bonhomme et al. (2003). The main feature of this technique is that power consumption during scan testing is minimized while constraints on scan routing are satisfied. In this paper, we propose a new version of this technique. The clustering process has been modified to allow a better distribution of scan cells in each cluster and hence lead to more important power reductions. Results are provided at the end of the paper to highlight this point and show that scan design constraints (length of scan connections, congestion problems) are still satisfied.

This paper presents an analysis of dynamic faults in core-cell of SRAM memories. These faults are the consequence of resistive-open defects that appear more frequently in VDSM technologies. In particular, the study concentrates on those defects that generate dynamic Read Destructive Faults, dRDFs. In this paper, we demonstrate that read or write operations on a cell involve a stress on the other cells of the same word line. This stress, called Read Equivalent Stress (RES), has the same effect than a read operation. On this basis, we propose to modify the well known March C-, which does not detect dRDFs, into a new version able to detect them. This is obtained by changing its addressing order with the purpose of producing the maximal number of RES. This modification does not change the complexity of the algorithm and its capability to detect the former target faults.

In this paper, we propose a technique for an exhaustive testing of all the delay faults in the logic architecture of symmetrical FPGAs, in a Manufacturing-Oriented Test (MOT) context. Previous techniques, concerning the test of delay faults in an FPGA, have mainly focused on delay faults on interconnexions. Our technique enables the detection of delay faults in the logic architecture and can be viewed as a complementary approach to the previous ones. The method uses the reconfiguration property of the FPGA to make easier the test of delay faults. The configuration scheme consists in chaining the logic cells or the Look-Up Tables (LUTs) in a specific way. The chain connects each LUT output to one input of the next LUT. We demonstrate that the test of all the delay faults can be done with only two configurations and a reduced test sequence.

This paper presents a new March test solution for detection of ADOFs (Address Decoder Open Faults), and resistive-ADOFs that are the consequence of resistive-open defects in address decoders of SRAM memories. In this study, we briefly analyze the test conditions and the March test requirements for these particular faults and we introduce some modifications to the well known March C- making it able to detect ADOFs and resistive-ADOFs, without increasing its complexity and its ability to detect the former target faults. The reformulation of March C-, called March iC-, is essentially based on introducing a particular address sequence and a particular read/write data sequence. The proposed March iC- extends the ability of March-based test solutions in detecting dynamic faults in SRAM memories.

This paper presents a comparative analysis of open (ADOF: Address Decoder Open Fault) and resistive open defects in address decoders of embedded-SRAMs. Such defects are the primary target of this study because they are notoriously hard-to-detect faults. In particular, we consider dynamic defects which may appear in the transistor parallel plane of address decoders. From this study, we show that test conditions required for ADOFs testing (sensitization and observation) can be partially used also for resistive open defect testing.

Detecting delay faults in SRAM-FPGAs can be done resorting to BIST. In this context, the objective of this paper is to analyse the timing behaviour of look-up tables (LUT) contained in FPGAs in both fault-free and delay faulty cases. We first show that the propagation delay of a LUT depends both on the transition pattern applied to its inputs and on the function implemented in it. This significant result questions the use of the basic assumption - the propagation delay of a LUT is independent of the function realized by it $considered in a number of recent papers. We next demonstrate that i) some physical defects in a LUT can change its propagation delay and ii) the delay due to a timing defect within the LUT varies depending on the location of the defect. We therefore conclude that unlike what is often done in existing FPGA BIST techniques, LUTs cannot be considered as programmable black boxes during test and testing their structure, either fully or partially, is needed to guarantee complete coverage of delay faults in the FPGA.

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Power consumption during scan testing is becoming a primary concern. In this paper, we present a novel approach for scan cell ordering which significantly reduces the power consumed during scan testing. The proposed approach is based on the use of a two-step heuristic procedure that can be exploited by any chip layout program during scan flip-flops placement and routing. The proposed approach works for any conventional scan design and offers numerous advantages compared with existing low power scan techniques. Reductions of average and peak power consumption during scan testing are up to 58% and 24% respectively for experimented ISCAS benchmark circuits.

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.

Test power is now a big concern in large system-on-chip designs. In this paper, we present a novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores. The proposed low power technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path. The idea is to reduce the clock rate on scan cells during shift operations without increasing the test time. Numerous advantages can be found in applying such a technique.

In this paper, we present a new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique during BIST.

A new BIST TPG design that is comprised of an Adjacency-based TPG plus a conventional pseudo-random TPG (i.e. a LFSR) is presented in this paper. When used to generate test patterns for test-per-clock BIST, it reduces the number of transitions that occur in the CUT and hence decreases the average and peak power consumption during testing. Moreover, the total energy consumption during BIST is also reduced since the test length produced by the mixed TPG is roughly the same as the test length produced by a classical LFSR-based TPG to reach the same fault coverage. Note that this TPG design has been developed to deal with strongly connected circuits with a small number of inputs.

Power consumption of digital systems may increase significantly during testing. In this paper, we propose a novel low power/energy Built-in Self Test (BIST) strategy based on circuit partitioning. The strategy consists of partitioning the original circuit into structural subcircuits so that each subcircuit can be successively tested through different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. The average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the subcircuits is not so far from the test length for the original circuit. The proposed strategy can be applied to either test-per-scan or test-per-clock BIST schemes by slightly modifying conventional TPG structures as illustrated in this paper. Results on ISCAS circuits show that average power reduction of up to 62%, peak power reduction of up to 57%, and energy reduction of up to 82% can be achieved at a very low area cost in terms of area overhead and with almost no penalty on the circuit timing.

In this paper, we propose a novel low power/energy built-in self test (BIST) strategy based on circuit partitioning. The goal of the proposed strategy is to minimize the average power, the peak power and the energy consumption during pseudo-random testing without modifying the fault coverage. The strategy consists in partitioning the original circuit into two structural subcircuits so that each subcircuit can be successively tested through two different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. the average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the two subcircuits is roughly the same as the test length for the original circuit. Results on ISCAS circuits show that average power reduction of up to 72%, peak power reduction of up to 53%, and energy reduction of up to 84% can be achieved.

This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The proposed approach is based on the reordering of test vectors of a given test sequence to minimize the average and peak power dissipation during test operation. For this purpose, the proposed technique reduces the internal switching activity by lowering the transition density at circuit inputs. The technique considers combinational or full scan sequential circuits and do not modify the initial fault coverage. Results of experiments show reductions of the switching activity ranging from 11% to 66% during external test application.

During self-test, the switching activity of the circuit under test is significantly increased compared to normal operation and leads to an increased power consumption which often exceeds specified limits. In the first part of this paper, we propose a test vector inhibiting technique which tackles the increased activity during test operation. Next, a mixed solution based on a reseeding scheme and the vector inhibiting technique is proposed to deal with hard-to-test circuits that contain pseudo-random resistant faults. From a general point of view, the goal of these techniques is to minimize the total energy consumption during test and to allow the test at system speed in order to achieve high fault coverage. The effectiveness of the proposed low energy BIST scheme has been validated on a set of benchmarks with respect to hardware overhead and power savings.

When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the serial shifting procedure. In the literature, different scan modification possibilities have been proposed for applying delay fault oriented deterministic test patterns. Another issue of the delay fault testing problem in scan-based sequential circuits is presented in this paper. The solution combines a BIST structure with the standard scan design.

With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this papel; we propose a post-mapping technique that can reduce the power dissipation by peeorming gate resizing.This technique consists of replacing some gates of the circuit with devices in a complete cell library having smaller area and, therefore, smaller gate capacitance with lower power consumption.The slack time of each gate in the circuit is first computed to determine the set of gates that can be down-sized.A global optimization procedure based on integer linear programming and the simplex method is then applied to determine the best overall gate resizing solution.Experimental results on benchmark circuits have shown a power reduction in the rangefrom 2.8 to 27.9 % compared to circuits without resizing.The most relevant features of our technique are that it is applicable to large digital circuits and gives an optimal resizing solution in a short computation time (no more than 15.8 seconds).

As delay testing using external testers requires expensive equipment, built-in self-test (BIST) is an alternative technique that can significantly reduce the test cost. In this paper, a BIST test pattern generator (TPG) design for the detection of delay faults is proposed. This TPG design produces test sequences having exactly the same robust delay fault coverage as single input change (SIC) test sequences obtained with the most efficient TPGs proposed before in the literature, but with a reduced test length and less area overhead. This reduction of the test length and area overhead is obtained by determining compatible inputs of the circuit under test (CUT), i.e. inputs that can be switch simultaneously without altering the robust test coverage.

This paper presents a GA-based technique to generate diagnostic-oriented delay tests for logic circuits. The aim is to produce a test sequence for a given circuit such that any couple of non-equivalent delay faults is distinguished by at least one rest pair belonging to the test sequence. For this purpose, we decided to preferably use a simulation-based approach with a directed search mechanism rather than developing a new deterministic ATPG. An appropriate fitness function that ranks population members according to their diagnostic capabilities has been defined, and genetic operators allowing a population to evolve during successive generations are presented. In order to have a diagnostic program providing near-optimal solutions, we combined the GA-based technique proposed in this paper with an existing post test diagnostic method for delay faults. Experimental results show that the genetic approach is effective for solving our diagnostic test generation problem, and point out the fact that the GA performs very well in comparison to a random test method.

Importance of delay testing is growing especially for high speed circuits. As delay testing using automatic test equipment is expensive, built-in self-test is an alternative technique that can significantly reduce the cost of delay testing. In this paper a new test pattern generation method for the detection of delay faults is proposed. It can be seen as a directed random generation technique, and uses some original concepts from machine learning to generate delay fault detecting test pairs. First, a set of random test vectors is generated. Next, a learning tool working on those vectors provides relevant features of delay fault detecting test pairs. Finally, a set of new test vectors that are consistent with those features is generated. A comparison with other test generation techniques has been done on several circuits, and has shown the efficiency of our solution in terms of test sequence length and delay fault coverage.

The goal of fault diagnosis is to identify the causes of device failures. Different techniques have been proposed for stuck-at fault diagnosis in combinational as well as sequential circuits. On the other side, diagnosis of delay faults has received attention for the first category of circuits, but not for synchronous sequential circuits. So, this paper concerns delay fault diagnosis for non-scan circuits. A preliminary version of the proposed method is first given. New concepts for allowing path tracing in the proposed diagnosis process (identification of self-masking) are also presented. As the method is based on path tracing through the sequential circuit, gate delay faults as well as path delay faults are considered and may be located in a faulty machine. Results of experiments on ISCAS-89 benchmark circuits are finally discussed.

Existing methodologies for determining delay fault coverages or for building up a delay fault dictionary are sometimes accurate, but rarely fast and easy to implement. Therefore, with the aim of removing these deficiencies, a new and more efficient fault simulation strategy for gate delay faults in combinational or scan-based circuits is presented. This method is based on a critical path tracing algorithm, thus avoiding the explicit simulation of each delay fault in the circuit. The novelty of the solution proposed to compute the detection threshold of a detectable delay fault increases the interest of the method, although it is computed approximately. Simulation results obtained for the ISCAS85 combinational benchmark circuits show the efficiency of the proposed method.>