The set theory of arithmetic decomposition is a method of designing complex addition/subtraction circuits at any radix using strictly positional, sign-local number systems. The specification of an addition circuit is simply an equation that describes the inputs and the outputs as weighted digit sets. Design is done by applying a set of rewrite rules known as decomposition operators to the equation. The order in which and weight at which each operator is applied maps directly to a physical implementation, including both multiple-level logic and connectivity. The method is readily automated, and has been used to design some higher radix arithmetic circuits. It is possible to compute the cost of a given adder before the detailed design is complete.>

A two-stage algorithm for fixed point, radix-16 signed-digit division is presented. The algorithm uses two limited precision radix-4 quotient digit selection stages to produce the full radix-16 quotient digit. The algorithm requires a two-digit estimate of the (initial) partial remainder and a three-digit estimate of the divisor to correctly select each successive quotient digit. The normalization of redundant signed-digit numbers requires accommodation of some fuzziness at one end of the range of numeric values that are considered normalized. A set of general equations for determining the ranges of normalized signed-digit numbers is derived. Another set of general equations for determining the precisions of estimates of the divisor and dividend are derived. These two sets of equations permit design tradeoff analyses to be made with respect to the complexity of the model division. The specific case of a two-stage radix-16 signed-digit division is presented. The staged division algorithm used can be extended to other radices as long as the signed-digital number representation used has certain properties.>

The properties of Hamming codes for error detection and correction can be extended from the binary parity check to addition, modulo 2r. Malfunctions in hardware during addition, modulo 2r, can be detected and corrected. Since carry-save and signed-digit addition, radix r, are included in addition, modulo 2r, this extension of Hamming codes makes possible new techniques for detection and correction of hardware malfunctions during signed-digit and carry-save addition.

Some conditions for distributivity of multiplication with respect to set addition are determined. In particular, distributivity holds if positive numbers are used, but does not hold for negative numbers in radix complement form. Use of simple recoding methods to achieve distributivity is not helpful, since costs of elementary multipliers and summing networks are increased. Distributivity does hold for the digit sets used for signed-digit arithmetic, and the requirement for distributivity provides guidance for the design of elementary multipliers.

A design tool for the decomposition of binary digital structures for addition and subtraction has been developed. A simplified theory reduces a complex structure to a collection of basic structures of one type, namely, a full adder. The simplified theory is applicable to the design of parallel counters and array multipliers. A general theory is used for decomposition to three types of basic structures, whose complexity is usually on the order of a half-adder. The general theory is applicable to redundant array multipliers and signed-digit adders.

This paper investigates the logical design of a redundant binary adder with two input digits and one output digit, all in the digit set {1, 0, 1}. Redundant binary arithmetic structures in which all digit sets are {1, 0, 1} were first discussed by Avizienis in 1961. Borovec studied the logical design of a class of such binary adders and subtracters in 1968. At that time, a variation of the adder/subtracter was overlooked. This paper studies the logical design of this variation. The sum digit is still a function only of the digits in three adjacent digital positions of the operands. "Coupled don't cares" are encountered, but have not introduced too much difficulty. The nine distinct formats (under permutation and negation) of representing three values with two bits given by Robertson are used. The simplest adder/subtracter designs from this variation are less complex than the simplest designs previously known.

The purpose of this paper is to demonstrate that representations of numbers other than positional notation may lead to practical hardware realizations for digital calculation of classes of algorithms. This paper describes current research in the use of continued fractions. Although practicality has not been demonstrated, theoretical results are promising.

The purpose of this paper is to demonstrate that representations of numbers other than positional notation may lead to practical hardware realizations for the digital calculation of classes of algorithms. It is the authors' opinion that practicality of the use of continued products has been demonstrated. This paper describes current research in the use of continued fractions. Although practicality has not been demonstrated, theoretical results are promising, and the results thus far are presented as a case study of the difficulties which arise when use of a new representation is attempted.

This paper relates previous analyses of the binary SRT division to the theory of multiplier recoding. Since each binary quotient digit has three possible values, the quotient resulting from the SRT division is in recoded form; in this paper it is shown that the recoding is a function of the divisor, and the method for determining the characteristic Boolean function of the recoding is presented. The relationship between the division and the recoding is established by scaling the division in such a way that the scaled "divisor" becomes a constant. Higher radix results are also discussed.

This paper describes a class of division methods best suited for use in digital computers with facilities for floating point arithmetic. The division methods may be contrasted with conventional division procedures by considering the nature of each quotient digit as generated during the division process. In restoring division, each quotient digit has one of the values 0,1, . . . , r -1, for an arbitrary integer radix r. In nonrestoring division, each quotient digit has one of the values -(r-1),. . ., -1, +1, . . ., +(r-1). For the division methods described here, each quotient digit has one of the values -n, -(n-1), . . ., -1, 0, 1, . . . n-1, n, where n is an integer such that ½(r-1)≤n≤r-1. A method for serial conversion of the quotient digits to conventional (restoring) form is given. Examples of new division procedures for radix 4 and radix 10 are given.

This paper describes a general method for modifying conventional binary asynchronous counters such that the counting register advances by any desired odd integer for each received count. The pertinent design features of conventional additive and subtractive asynchronous counters are reviewed. Simplification of the design of a counter which advances by an odd integer is achieved through use of a set of alternately additive and subtractive subcounters. An example of the logical design of a counter which advances by 13 is presented.