This paper describes a quadrature direct digital frequency synthesizer (QDDFS) architecture based on a new phase-to-sine conversion technique. The proposed technique uses polynomial interpolation and rotational transformation in a fine/coarse approach, achieving high-resolution output with a wide spurious-free dynamic range (SFDR). The QDDFS with this technique requires small-sized lookup tables and a simple computational engine. The fine/coarse decomposition significantly reduces the size of required lookup tables, and the polynomial interpolation enables accurate approximation of cosine and sine values. Two prototype QDDFS ICs were fabricated in 0.35-/spl mu/m CMOS. The final prototype IC produces 16-b cosine and sine outputs with a spectral purity greater than 100-dB. It has a frequency tuning resolution of 0.03-Hz at a 150-MHz sampling rate and consumes 350-mW with a 3.0-V power supply.

This paper describes a digital timing synchronization method for the CAP-based VDSL system. An adaptive loop filter with digitally controlled loop gain is proposed for jitter performance improvement. The proposed loop filter allows both fast locking and low steady state jitter. A digital spectral line method is used for robust timing extraction. Simulation results show that RMS timing jitter is less than 0.4% of the symbol period even for the worst case channel and synchronization is established within 400 symbol periods. The VDSL system is implemented in a 0.6 /spl mu/m CMOS technology, and tested. The measured peak-to-peak timing jitter is about 0.1% of the symbol period, which makes the VDSL system receive data up to 52 Mbps over the telephone wire.

A new baseband clock recovery algorithm for /spl pi//4-QPSK modulated signals is presented. Conventional data-aided algorithm for /spl pi//4-QPSK modulated signals achieves good jitter performance, but suffers from slow initial acquisition and are prone to the potential error accumulation. Several non-data-aided timing recovery algorithms showing jitter performance approaching that of data-aided ones are proposed. Rayleigh fading and Gaussian noise are considered in the simulation. Simulation results show that the proposed non-data-aided algorithms satisfy the necessary requirements under Rayleigh fading.

This paper presents 16-bit DSP processor and system for baseband and voiceband processing of IS-136 digital cellular telephony that is North America TDMA standard. The DSP, named MIGHTI, that is designed for mobile communication applications, has some special instructions that allow instruction pipelining for the compound operations. MIGHTI includes a low-power 16 K-word flexible port fullcustom memory. With MIGHTI, IS-136 baseband and voiceband processing that normally requires 45 MIPS in a conventional DSP, is performed in just 36 MIPS. The system developed for baseband and voiceband processing does meet the requirements of the IS-136 standard.

Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth is preferred to being adjusted accordingly. In this paper, a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. This algorithm, based on the recursive least squares (RLS) criterion, suggests an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithm can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drives that require a short initial preamble period.

This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of tile PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications. Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.

We propose a DPLL (digital phase-locked loop) with time-varying loop gains which are derived from the RLS method. This method, in contrast to the one based on the standard Kalman filtering algorithm, is appropriate for the situation where no statistics are known. If the forgetting factor in the RLS method is constant, the acquisition performance only improves in the initial stage. However, with the variable forgetting factor adaptive to the measurements, the DPLL shows excellent acquisition and tracking performance under a non-stationary environment which are comparable to that based on the adaptive Kalman filter with lock detection algorithm.

An approach to the derivation of variable loop gain sequences of dual-loop digital phase-locked loop (DPLL) is developed based on some modifications of the Kalman filtering formulation. It is shown that optimal loop gain sequences which are independent of measurement noise statistics can be obtained under a deterministic source model. Computer simulation results demonstrate that the adaptive dual-loop DPLL designed by using the proposed method is more robust to noise variations than the adaptive DPLL of Driessen (see ibid., vol.47, p.673-75, 1994).

No abstract available.

A salient adaptive carrier recovery with a multi-order Digital Phase-Locked Loop (DPLL) based on Kalman filtering is presented in this paper. Using optimal loop gain sequence, that is Kalman gain sequence, for various optimization criteria, the proposed DPLL achieves fast phase acquisition and low phase jitter. The loop gain sequence optimized under the Least Squares (LS) criterion shows enough phase tracking capability under severe fading and can be used for mobile communication applications. Finally, the multi-order DPLL allows robust stability and bandwidth control and achieves zero phase offset.

This paper presents an analytical model for timing jitter accumulation in ring-oscillator based phase-locked-loops (PLL). The timing jitter of the system is shown to depend on the jitter in the ring-oscillator and an accumulation factor which is inversely proportional to the bandwidth of the phase-locked-loop. Further analysis shows that for delay-locked-loops (DLL), which use an inverter delay chain that is not configured as a ring-oscillator, there is no noise enhancement since noise jitter events do not contribute to the starting point of the next clock cycle. Finally, theoretical predictions for overall jitter are compared to behavioral simulations with good agreement.>

in this paper the effects of thermal noise in transistors on timing jitter in CMOS ring-oscillators composed of source-coupled differential resistively-loaded delay cells is investigated. The relationship between delay element design parameters and the inherent thermal noise-induced jitter of the generated waveform are analyzed. These results are compared with simulated results from a Monte-Carlo analysis with good agreement. The analysis shows that timing jitter is inversely proportional to the square root of the total capacitance at the output of each inverter, and inversely proportional to the gate-source bias voltage above threshold of the source-coupled devices in the balanced state. Furthermore, these dependencies imply an inverse relationship between jitter and power consumption for an oscillator with fixed output period. Phase noise and timing jitter performance are predicted to improve at a rate of 10 dB per decade increase in power consumption.>